View 1990815_316373.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
DSLAM
DSLAM REFERENCE DESIGN: CORE CARD
RELEASED Issue 4 December 2000
(c) 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Phone 604.415.6000 FAX 604.415.6200 This document is for the internal use of PMC-Sierra, Inc. and PMC-Sierra, Inc. customers only. In any event, no part of this document may be reproduced in any form without the express written consent of PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
REVISION HISTORY Issue No. 4 Issue Date December 2000 Details of Change Replaced "metadriver" with "VORTEX Chipset Driver" for consistency with software driver documents. Updated LVDS hot swap explanation and cell transfer, which may be affected by setting OCAEN bit in register 0x0A of the S/UNI-DUPLEX. Register write sequence is required to enable OCAEN at the very end of the chipset activation. The sequence is already implemented with the VORTEX Chipset Driver on CD-ROM Ver 3.0. Document rewritten and updated for Issue 3. Updated schematics Issue 3. Included PCB layer plots. Added test results from FTP on Core Card Issue 3. Updated BOM. Added appendix with software example. Paper design errata-document. This Reference Design Issue 2 has no Core Card PCB manufactured. First Issue. Core Card Issue 1 build.
3
September 2000
2 1
December 1999 August 1999
(c) 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Phone 604.415.6000 FAX 604.415.6200 This document is for the internal use of PMC-Sierra, Inc. and PMC-Sierra, Inc. customers only. In any event, no part of this document may be reproduced in any form without the express written consent of PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
CONTENTS
1. 2. 3. OVERVIEW ....................................................................................................................... 1 DSLAM CORE CARD FEATURES ................................................................................... 2 TYPICAL DSLAM APPLICATION WITH CORE CARD..................................................... 3 3.1. 3.2. 4. Compact PCI (cPCI) Development Shelf ............................................................. 4 DSLAM Reference Design Core Card Architecture ............................................. 4
CORE CARD FUNCTIONAL EXPLANATION................................................................... 7 4.1. Core Card Block Diagram .................................................................................... 7 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.5. 4.1.6. 4.1.7. 4.1.8. 4.2. Block Diagram Drawing........................................................................... 7 VORTEX Chipset..................................................................................... 8 LVDS Interface ........................................................................................ 8 PCI Bridge ............................................................................................... 9 Hot Swap Controller ................................................................................ 9 Ejector Handle and LED.......................................................................... 9 CPLD ....................................................................................................... 9 RAMs..................................................................................................... 10
DSLAM High-Speed LVDS Serial Interface........................................................ 11 4.2.1. 4.2.2. Example of LVDS Routing on Core Card .............................................. 11 LVDS Transmitters vs. Hot Swap .......................................................... 12
4.3. 5.
8kHz Interface .................................................................................................... 12
CORE CARD CHIPSET OVERVIEW .............................................................................. 15 5.1. PM7324 S/UNI-ATLAS ....................................................................................... 15 5.1.1. 5.1.2. 5.2. Ingress SRAM ....................................................................................... 16 Egress RAM .......................................................................................... 18
S/UNI-APEX ....................................................................................................... 19 5.2.1. 5.2.2. 5.2.3. Functional Description........................................................................... 19 Context Memory SSRAM Interface ....................................................... 23 Cell Buffer SDRAM Interface................................................................. 24
5.3. 5.4. 5.5.
S/UNI-VORTEX .................................................................................................. 25 S/UNI-DUPLEX .................................................................................................. 28 CPCI Bridge........................................................................................................ 29
iii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
5.5.1. 5.5.2. 6.
PCI9054 PCI Bridge .............................................................................. 29 SEEP Basics ......................................................................................... 29
SIGNAL FLOW ON THE CORE CARD IN BRIEF .......................................................... 30 6.1. 6.2. Upstream Direction............................................................................................. 30 Downstream Direction ........................................................................................ 31
7.
HOT SWAP...................................................................................................................... 32 7.1. 7.2. 7.3. cPCI and Power Rail Hot Swap.......................................................................... 32 LVDS Hot Swap.................................................................................................. 34 Blue LED and Microswitch Control..................................................................... 35
8.
CPCI INTERFACE, PCI BRIDGE AND CPLD................................................................. 36 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. Control Interface Block Diagram ........................................................................ 36 PCI Bridge - CPLD Interface ............................................................................. 38 Major Control Lines Between S/UNI-APEX, CPLD and PCI9054 Interface....... 38 Address Mapping ............................................................................................... 40 PLX PCI9054 Address Spaces........................................................................... 41 Card ID Number ................................................................................................. 41 Serial EEPROM Load Registers ........................................................................ 41 CPLD .................................................................................................................. 44 8.8.1. 8.8.2. 8.8.3. 8.8.4. 8.8.5. 8.8.6. 8.9. Local Bus Memory Map......................................................................... 45 CPLD Registers..................................................................................... 46 Alarms And Interrupts............................................................................ 49 8 kHz Channel....................................................................................... 49 Address Decoding and Chip Enable ..................................................... 49 CPLD Type ............................................................................................ 49
CPLD Block Diagram ......................................................................................... 50
9.
CONNECTORS ON CORE CARD.................................................................................. 51 9.1. CPCI Connectors ............................................................................................... 51 9.1.1. 9.1.2. 9.1.3. 9.2. 9.3. J1 on Core Card .................................................................................... 51 J2, J3, and J4 on Core Card ................................................................. 51 J5 on Core Card .................................................................................... 51
LVDS Interface on the LVDS-backlane .............................................................. 51 LVDS Interface on the Front Panel..................................................................... 52
iv
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
9.4. 9.5. 9.6. 9.7. 9.8. 9.9. 9.10. 9.11. 9.12. 9.13. 10.
CPLD Programming Interface on J34 ................................................................ 52 25 MHz Output on J45 ....................................................................................... 52 RESET Header J64 ............................................................................................ 52 8 kHz Interface on J65 and J72.......................................................................... 52 JTAG Interface on J66........................................................................................ 53 Mictor Connectors J70 and J71.......................................................................... 53 Clock Control Header J73 .................................................................................. 53 Optional Reset to CPLD Header J74 ................................................................. 53 Ejector Handle Switch Header TP115 ................................................................ 54 Miscellaneous Test Points .................................................................................. 54
LVDS INTERFACE .......................................................................................................... 55 10.1. 10.2. 10.3. LVDS Front Panel Interface................................................................................ 55 LVDS Eye Pattern at Jumper Field Tests ........................................................... 57 LVDS Eye Pattern over LVDS-Backplane Tests................................................. 58
11.
BUS TERMINATION EXAMPLES ................................................................................... 61 11.1. 11.2. 11.3. 11.4. 11.5. Microprocessor Bus Termination ........................................................................ 61 Downstream Any-PHY Bus Termination............................................................. 63 Upstream/Downstream UL2 Bus Termination .................................................... 64 S/UNI-APEX - S/UNI-ATLAS Bus Termination .................................................. 66 RAM Bus Termination......................................................................................... 67
12.
HARDWARE.................................................................................................................... 74 12.1. 12.2. 12.3. 12.4. 12.5. 12.6. Card Form .......................................................................................................... 74 Front Plate on Core Card ................................................................................... 74 LEDs On the Front Plate .................................................................................... 75 Printed Circuit Board Stack ................................................................................ 77 Key Coding on the J1 Connector ....................................................................... 78 Power Supply Specification ................................................................................ 78 12.6.1. Core Card .............................................................................................. 78 12.6.2. S/UNI-DUPLEX and S/UNI-VORTEX.................................................... 79
13.
SOFTWARE .................................................................................................................... 80 13.1. 13.2. System Processor Requirement......................................................................... 80 DSLAM Operating System ................................................................................. 80
v PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
13.3. 13.4.
Device Drivers .................................................................................................... 80 Example of VORTEX Chipset Setup ................................................................. 80 13.4.1. APEX Setup........................................................................................... 80 13.4.2. APEX Operations .................................................................................. 81 13.4.3. DUPLEX and VORTEX Setup............................................................... 81 13.4.4. DUPLEX And VORTEX Operation ........................................................ 81 13.4.5. ATLAS Setup ......................................................................................... 81 13.4.6. ATLAS Operations................................................................................. 82 13.4.7. Important Notes For Chipset Level Setup ............................................. 82
13.5. 13.6. 13.7. 14.
Firmware............................................................................................................. 82 Programmable Logic Devices ............................................................................ 82 System Control ................................................................................................... 82
APPENDIX A: TESTS EXAMPLE UTILIZING CORE CARD DRIVER ........................... 84 14.1. 14.2. 14.3. Register and RAM Test with VORTEX Chipset Driver ....................................... 84 Cell Data Path with Internal Loopback Test ...................................................... 85 External Loopback Test ...................................................................................... 87 14.3.1. Sub Test 1: Downstream/Upstream on Sixteen Channels. ................... 87
15. 16. 17.
APPENDIX B: VOLTAGE DISCHARGE ON TRI-STATED BUS ..................................... 92 APPENDIX C: EXAMPLE OF SEEP READING ON RESET ......................................... 95 APPENDIX D: LOCAL BUS TIMING EXAMPLES ......................................................... 96 17.1.1. Timing Example for Read from S/UNI-APEX ........................................ 96 17.1.2. Timing Example for Write to S/UNI-APEX............................................. 97 17.1.3. Timing Example for Read from S/UNI-DUPLEX ................................... 98 17.1.4. Timing Example for Write to S/UNI-DUPLEX........................................ 99
18. 19. 20. 21.
APPENDIX E: VHDL FOR CPLD .................................................................................. 100 APPENDIX F: BILL OF MATERIAL ............................................................................... 109 APPENDIX G: SCHEMATIC DIAGRAMS ..................................................................... 113 APPENDIX H: LAYOUT................................................................................................. 115 21.1. 21.2. Drawing Summary Report ................................................................................ 115 X-Y Coordinates for Issue 3 Board................................................................... 116
22.
APPENDIX I: GLOSSARY............................................................................................. 126
vi PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
LIST OF FIGURES
FIGURE 1. FIGURE 2. FIGURE 3. FIGURE 4. FIGURE 5. FIGURE 6. FIGURE 7. FIGURE 8. FIGURE 9. FIGURE 10. FIGURE 11. FIGURE 12. FIGURE 13. FIGURE 14. FIGURE 15. FIGURE 16. FIGURE 17. FIGURE 18. FIGURE 19. FIGURE 20. FIGURE 21. FIGURE 22. FIGURE 23. FIGURE 24. FIGURE 25. FIGURE 26. FIGURE 27. FIGURE 28. FIGURE 29. FIGURE 30. DSLAM Reference Design Shelf Architecture......................................... 3 The Core Card Architecture..................................................................... 4 The Core Card Top View ......................................................................... 6 Core Card Block Diagram ....................................................................... 7 LVDS on Core Card............................................................................... 11 Example of 8kHz Clock Flow on Core Card.......................................... 13 Example of Received 8 kHz Time Reference ....................................... 14 S/UNI-ATLAS SRAM VC Table Addressing .......................................... 16 VC Ingress S/UNI-ATLAS-SSRAM Connection .................................... 17 VC Egress S/UNI-ATLAS-SSRAM Connection..................................... 18 Dual Bank Configuration for ZBT SSRAM ............................................ 24 Single Bank SDRAM 4 MB for 64 k Cells.............................................. 25 Example of a Hot-Swap Circuit ............................................................. 32 LED_SWITCH\I Line Siganl .................................................................. 35 cPCI and Local Bus Microprocessor Interface...................................... 36 S/UNI-APEX, CPLD, and the Local Bus Microprocessor Interface ...... 39 CPLD Block Diagram ............................................................................ 50 8 kHz Interface ...................................................................................... 53 LVDS Pinout on DSLAM Cards ............................................................. 55 LVDS Header Straps ............................................................................. 56 Wave Shapes with a Single Active LVDS Transmitter........................... 57 LVDS Over Backplane Test Connections .............................................. 59 LVDS at Core Card and Line Card with LVDS backplane..................... 59 Microprocessor Bus Termiantion ........................................................... 61 Examples of Signal Integrity on uP Bus ................................................ 62 Any-PHY Bus Termiantion..................................................................... 63 Example of Signal Integrity Downstream at VORTEX-1 ....................... 64 Upstream/Downstream UL2 Bus Termination ....................................... 65 Example of Signal Integrity Upstream at VORTEX-1............................ 66 S/UNI-APEX - S/UNI-ATLAS Bus Termiantion ..................................... 67
vii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
FIGURE 31. FIGURE 32. FIGURE 33. FIGURE 34. FIGURE 35. FIGURE 36. FIGURE 37. FIGURE 38. FIGURE 39. FIGURE 40. FIGURE 41. FIGURE 42. FIGURE 43. FIGURE 44. FIGURE 45. FIGURE 46. FIGURE 47. FIGURE 48. FIGURE 49.
RAM Bus Termiantion............................................................................ 68 Waveforms at S/UNI-APEX at 80 MHz ................................................. 69 Waveforms at SDRAM at 80 MHz......................................................... 70 Waveforms at SDRAM at 80 MHz......................................................... 71 Waveforms at S/UNI-APEX at 80 MHz ................................................. 72 Waveforms at SSRAM at 50 MHz ......................................................... 73 Front Plate for Core Card ...................................................................... 74 Example of LEDs Placement ................................................................ 76 PCB Cross-section ................................................................................ 77 Data Path with Internal Loopback ......................................................... 86 External Loopback with ATM over DS-3 Tester..................................... 87 Voltage Discharge on Hi-Z Bus Line ..................................................... 92 Voltage Discharge on Hi-Z Bus Line with Noise.................................... 93 Example of SEEP Reading Upon PCI Reset ........................................ 95 Example of SEEP Reading Upon PCI Reset ........................................ 95 Example Read from the S/UNI-APEX at 25 MHz.................................. 96 Example Write to APEX Cycle on Local Bus at 25 MHz ....................... 97 Example Read from the S/UNI-DUPLEX .............................................. 98 Example Write to the S/UNI-DUPLEX................................................... 99
viii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
REFERENCES PMC-Sierra, Inc. DSLAM Hardware 1. PMC-Sierra Inc., PMC-1990832, "DSLAM Reference Design: System Design", Issue 3, September 2000
2.
PMC-Sierra Inc., PMC-1990354, "DSLAM Reference Design: Line Card", Issue 3, September 2000 PMC-Sierra Inc., PMC-1990474, "DSLAM Reference Design: WAN Card", Issue 3, September 2000 PMC-Sierra, Inc., PMC-971154, " Saturn User Network Interface ATM Layer Solution Data Sheet" (S/UNI-ATLAS, PM7324), Issue 7, January 2000. PMC-Sierra Inc., PMC-1990816, "DSLAM Apps Note: Signal Integrity and Timing Simulation for the VORTEX Chipset", Issue 1, September 2000 PMC-Sierra Inc., PMC-1981025, "S/UNI-VORTEX and S/UNI-DUPLEX Technical Overview", Issue 2, June 1999 PMC-Sierra, Inc., PMC-981224, " ATM/Packet Traffic Manager and Switch Data Sheet" (S/UNI-APEX, PM7326), Issue 6, April 2000.
3.
4.
5.
6.
7.
PMC-Sierra, Inc. DSLAM Software
8.
PMC-Sierra Inc., PMC-1980585, S/UNI -ATLAS Programmer's Guide and Example Software, Issue 2, Feb. 1999 PMC-Sierra Inc., PMC-1991727, S/UNI-APEX Device Driver Design, Issue 2, May 2000 PMC-Sierra Inc., PMC-1990786, S/UNI-VORTEX Driver Manual, Issue 1, Aug. 1999 PMC-Sierra Inc., PMC-1990799, S/UNI-DUPLEX Driver Manual, Issue 1, Aug. 1999 PMC-Sierra Inc., PMC-1991454, S/UNI-APEX H/W Programmer's Guide, Issue 2, April 2000 PMC-Sierra Inc., PMC-1991578, S/UNI-APEX Device Driver Release Notes, Issue 2, June 2000 PMC-Sierra Inc., PMC-2000781, VORTEX Chipset Driver Release Notes, Issue 1, August 2000.
9.
10.
11.
12.
13.
14.
ix PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Industry Standards
15.
Bell Communications Research, "SONET Transport Systems: Common Generic Criteria," GR-253-CORE, Issue 2, December 1995. Bell Communications Research, "Clocks for the Synchronized Network: Common Generic Criteria" GR-1244-CORE, Issue 1, June 1995. ITU-T, "The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH)", March 1993. PCI Industrial Computers manufacturers Group (PICMG), "CompactPCI Specification", PICMG 2.0 R2.1, September 2, 1997. PCI Industrial Computers manufacturers Group (PICMG), "Hot Swap Specification", PICMG 2.1 R1.0, May 14, 1998. (Draft - not approved) ADSL Forum, Web Page, http://www.adsl.com Montrose, Mark I., "Printed Circuit Board Design Techniques for EMC Compliance", IEEE Press, 1996.
16.
17.
18.
19.
20. 21.
x PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
1.
OVERVIEW The purpose of the Reference Design document set is to assist engineers in designing their products using the PMC-Sierra VORTEX chipset. The DSLAM Reference Design is composed of these four main documents:
* * * *
DSLAM Reference Design: System Design DSLAM Reference Design: Core Card DSLAM Reference Design: WAN Card DSLAM Reference Design: Line Card
The DSLAM Reference Design: System Design document provides an overview of the DSLAM Reference Design system architecture. The remaining documents describe the functionality and implementation specific details for each individual card. This document specifically describes the design for the DSLAM Core Card. A block diagram illustrates the Core Card design. A description is then given for the functional blocks of the design. A detailed implementation description then follows. The appendixes contains additional information, such as, schematics, bill of material, and CPLD VHDL source.
1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
2.
DSLAM CORE CARD FEATURES The Digital Subscriber Line Access Multiplexer (DSLAM) Core Card features:
* * *
ATM traffic policing and traffic shaping Small-scale traffic management (switching) with the S/UNI-APEX A high-speed Low Voltage Differential Signal (LVDS) interface that:
* *
Provides data rates up to 200Mb/s Allows manual selection of transmission over a backplane or through cables. Supports one-to-one (1:1) protection switching
* *
Support for clock synchronization to either the DS-3 network or the line side interface Front panel LEDs to indicate:
* *
*
Power supply status LVDS signal status
*
On-board hot swap controller to monitor the current flow onto the board for live insertion and extraction Compact PCI (cPCI) compatibility
*
2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
3.
TYPICAL DSLAM APPLICATION WITH CORE CARD Figure 1 shows a typical application for the S/UNI-DUPLEX, S/UNI-VORTEX, S/UNI-APEX, and the S/UNI-ATLAS. Figure 1. DSLAM Reference Design Shelf Architecture
LVDS over Backplane
Core Card 1 Operational
VORTEX-1 S/UNIAPEX S/UNIATLAS
LVDS over Backplane
DUPLEX
P1 P2
P1 P2 P8 P1 P2 P8
DUPLEX
P1 P2
P1 P2
Line Card 1
VORTEX-2
SRAM
SRAM
WAN Card 1
DUPLEX
P2
P1 P2 P8 P1 P2 P8
VORTEX-1
P1
DUPLEX
Line Card 2
P1 P2
P1 P2
VORTEX-2
SRAM
SRAM
WAN Card 2 Core Card 2 Hot Standby
LVDS over Cable DUPLEX
P1 P2
Line Card 16
Optional equipment mounted on additional shelf
Host CPU Card
CPCI Bus to Core Card 1 and Core Card 2 only
Figure 1 shows two Core Cards in protective mode. The lower card is the hot stand-bycard that allows one-to-one backup for the operating Core Card. Also, this block diagram shows a DSLAM development shelf that is equipped with a custom LVDS-backplane, two Line Cards, two WAN Cards, and two Core Cards. A single host CPU card controls Core Cards only. Additional Line Cards can be mounted on a separate shelf with LVDS over cables. Line Cards and WAN Cards, built for the DSLAM Reference Design, have an embedded microprocessor without communication to the cPCI bus.
3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
DUPLEX
S/UNIAPEX
S/UNIATLAS
DUPLEX
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
3.1.
Compact PCI (cPCI) Development Shelf The DSLAM Reference Design for the Core Card is based on a cPCI shelf allowing standardization of interfaces and physical card forms. A custom-made LVDS-backplane is developed demonstrating the LVDS interface functioning over the backplane. LVDS can also be connected with cables through the front plate connectors. The shelf-to-shelf LVDS is implemented using the front plate connectors exclusively. Two Core Cards are used to provide a hot stand-by, as required by the Telcos. The basic DSLAM development shelf is an 8-slot entity. A 16-slot shelf can be also supported with a single Reference Design Core Card (with an optional hot stand-by card for protection switching).
3.2.
DSLAM Reference Design Core Card Architecture Figure 2 shows the DSLAM Reference Design and Core Card Reference Design that is built around a single S/UNI-ATLAS architecture. Figure 2.
Any-PHY, Transmitted Data VORTEX 1
The Core Card Architecture
Utopia L2, Received Data
UL1
Loop Any-PHY WAN Any-PHY RX TX Master Master Downstream
OAM only
Ingress Out, Slave
Ingress In, Master
Policing
VORTEX 2
DUPLEX
Line Cards
S/UNI-APEX
Upstream
S/UNI-ATLAS
UL2 Egress In Slave Egress Out Master Utopia L2
OAM
Loop Any-PHY RX Slave
WAN Any-PHY TX Master
WAN Card
VORTEX n
SSRAM context
SDRAM cell buffer Downstream Upstream
SSRAM VC table
The S/UNI-APEX and S/UNI-ATLAS are the core of the design. The downstream and upstream cells are interfaced to the S/UNI-ATLAS through the same Ingress In, Masterport. The Loop Any-PHY RX, Slave port on the S/UNI-APEX is connected to WAN direction Egress Out, Master allowing OAM cell flow (RDI from the S/UNI-ATLAS towards downstream). The S/UNI-APEX switches cells to Loop Any-PHY TX, Master or to WAN Any-PHY TX, Master ports as required per
4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
cell destination. The Core Card interface to the Line Cards is through a set of S/UNI-VORTEX devices. The Core Card interface to the network is through the S/UNI-DUPLEX, which provides an LVDS link to the WAN Card. In the upstream direction, the S/UNI-ATLAS takes cells from the Line Cards and performs a look-up, based on the PHY number, VPI, and VCI that are used to identify the associated connection. Once the connection is identified, the cell is processed according to the configuration of the connection. In this application, the S/UNI-ATLAS performs the header translation, per-PHY and per-VC policing, performance monitoring, and fault management. Prepend and postpend are used to navigate the cell. In the downstream direction, the S/UNI-ATLAS accepts the cells coming from a WAN Card and a direct look-up is performed to identify the connection. The cell is then processed according to the configuration in the context table for that connection (cell is tagged). The header translation and OAM processing can be done at the ingress. The tagged cell is sent to the S/UNI-APEX WAN Any-PHY RX, Master port. The S/UNI-APEX puts the cell into a queue and sends it to either Loop Any-PHY TX, Master or WAN Any-PHY TX, Master ports. The tag determines the port. If the cell destination is loop side, then the cell goes through the Loop Any-PHY TX, Master port to one of the S/UNI-VORTEX multiplexers, where the destination channel matches the tag number. The cell is passed to one of 32 queues for transmission by the appropriate PHY. The AIS cell coming from the loop (upstream) arrives at the S/UNI-ATLAS Ingress In port. The S/UNI-ATLAS generates the RDI cell with the tag that corresponds to the port where the AIS cell arrived. The RDI cell is sent to the Egress Out port and then arrives at the S/UNI-APEX slave port, Loop Any_PHY RX, only if the tag matches the loop side destination. The S/UNI-APEX puts the RDI cell into a queue and sends the cell through the Loop Any-PHY TX, Master port to one of the S/UNI-VORTEX multiplexers, where the destination channel matches the tag number. The network management entity has to assign unique port (channel) numbers to all S/UNI-DUPLEX and S/UNI-VORTEX devices attached to the Utopia L2 bus. The Core Card picture is shown in Figure 3 below.
5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 3.
Core Card Top View
6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
4. 4.1.
CORE CARD FUNCTIONAL EXPLANATION Core Card Block Diagram This section briefly describes the Core Card block diagram. 4.1.1. Block Diagram Drawing
Figure 4 shows the Core Card layout block diagram. Figure 4. Core Card Block Diagram
16 pairs LVDS Headers 4 pairs VORTEX 1 LVDS
Up/down stream, UL2
DUPLEX
LVDS
4 pairs
LVDS over cable
Clock 25MHz Downstream, Any-PHY
S/UNI ATLAS
SSRAM
VORTEX 2
LVDS
8kHz
8kHz PLL
16 pairs
1394 Connectors
SSRAM
SSRAM
UL1/UL2
UL2
Clock 25MHz ATLAS APEX VORTEX1 VORTEX2 DUPLEX LED 8 kHz
Clock 80MHz
cPCI Bridge
Hot Swap Controller
LED Ejector Switch
J1
Core Card
The block diagram shows the PMC Sierra chipset associating with RAMs, clocks, PCI bridge, and CPLD. LVDS connectors at the front and at the back of the Core Card allow an interface to the high-speed LVDS signals (up to 200 Mbps). The PCI bus and power (+5 V and +3.3 V) are connected through J1. A system synchronization 8 kHz clock (stratum clock) can be interfaced at the internal headers.
7 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PCI Bus over cPCI backplane
S/UNI APEX
SDRAM SDRAM
Address CPLD
LVDS over LVDS-backplane
J5
1394 Connectors
SSRAM
16 pairs
SSRAM
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
4.1.2.
VORTEX Chipset
Five chips shown in the block diagram above create a single entity called VORTEX chipset, including the S/UNI-ATLAS, S/UNI-APEX, S/UNI-DUPLEX, and S/UNI-VORTEX. The VORTEX chipset, and Core Card as well, provides ATM traffic policing (S/UNI-ATLAS), ATM cell traffic management (S/UNI-APEX), and ATM cell multiplexing (S/UNI-VORTEX and S/UNI-DUPLEX). In the downstream direction, the S/UNI-APEX sends data to the S/UNI-VORTEX and then to the Line Card(s) through the PMC-Sierra Any-PHY interface. The Any-PHY interface supports a bandwidth of up to 800 Mb/s and allows for 2048 channel addressing. The data format is an ATM cell with a prepended single address word. On the user (loop) side, the Core Card provides an interface through the S/UNIVORTEX-1 or S/UNI-VORTEX-2 to the Line Cards. On the network side, the Core Card provides an interface through a S/UNI-DUPLEX to the WAN Card. Both interfaces are LVDS type with data transfer rates up to 200 Mb/s. The S/UNI-ATLAS provides traffic policing and OAM functionality. A single entry port to the S/UNI-ATLAS of both upstream and downstream cells (specific to this Reference Design) provides easy traffic policing - the S/UNI-ATLAS implements that function in the Ingress direction only. The VORTEX chipset is described in more details later in this document. 4.1.3. LVDS Interface
The Core Card provides an interface for the LVDS from the front plate or from the LVDS-backplane. The LVDS interface at the front panel allows access to eight ports on the S/UNI-VORTEX-1, eight ports on the S/UNI-VORTEX-2, and two ports on the S/UNI-DUPLEX. LVDS over the backplane provides an interface to eight ports on the S/UNI-VORTEX-1 and two ports on the S/UNI-DUPLEX. Space limitations prevent all LVDS ports of the S/UNI-VORTEX-2 from being accessible at the back connector J5. The LVDS connectors were chosen to be an IEEE Firewire type that supports a data rate in excess of 200 Mb/s. The LVDS drivers, receivers, copper traces, and connectors are designed to work in 50/100 ohm environment. Individual trace and driver is designed for 50 ohm characteristic impedance. The differential LVDS lines at the receiver inputs are loaded with external 100 ohm resistors. More on LVDS can be found in sections 4.2, 9.2, 9.3 and 10 in this document.
8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
4.1.4.
PCI Bridge
The Core Card does not have an on-board microprocessor. The PCI bus host processor card provides an interface to the Core Card through a cPCI bridge device, which only uses a read/write (burst) register sequence and interrupt service. The cPCI bus does not carry payload data, which enables the host CPU to maintain all DSLAM cards through the cPCI bus without burden of ATM traffic over cPCI. If required, cells can be inserted into traffic through the cPCI interface. The hot swap compatible PCI bridge (PLX PCI9054) is used as the PCI bus interface. The bridge operates in multiplexed mode on the local bus side. The PCI9054 provides an interface to a CPLD for address decoding (chip enable). The local bus speed is set at 25 MHz, which allows the microprocessor interface on all devices to run at the optimum speed. The PCI9054 requires a serial EEPROM (SEEP) to boot on power-up (or reset). 4.1.5. Hot Swap Controller
The hot swap controller LTC1645, and discrete components are used to make the Core Card hot swap compatible. This device is accompanied with the LTC1326 supply voltage monitor and reset line generator. 4.1.6. Ejector Handle and LED
The ejector handle has a built-in microswitch that toggles when the ejector changes position. The activity is detected by the cPCI bridge, which in turn notifies the host CPU about the status change. A blue LED signals the card's "not-ready-yet" status upon insertion or the card's readiness for removal. NOTE: This functionality requires specific software driver, which is not supported by the PMC-Sierra VORTEX Chipset Driver. Also, the host CPU card must have hardware provision to detect activities on the ENUM# line. 4.1.7. CPLD
A CMOS Programmable Logic Device (CPLD) is used to provide address decoding, LED latches, interrupt latches, and 8 kHz clock routing. The Xilinx XC95144 was chosen for this design. The CPLD is in-circuit programmable through a header connector.
9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
4.1.8.
RAMs
The S/UNI-ATLAS and the S/UNI-APEX need fast RAMs to buffer large amounts of data. The S/UNI-APEX needs both SDRAM and SSRAM. Both RAMs operate at 80 MHz. The Reference Design shows oversized RAMs due to chip availability and system verification purposes. The Core Card cell throughput can be supported with smaller RAM sizes. The cell buffer SDRAMs are at 16 MBytes in two integrated circuits. The context memory NBT (ZBT) SSRAM is shown as 4 MBytes that use two integrated circuits. Also, RAM size depends on availability of RAM chips at the time the Core Cards are assembled. The S/UNI-ATLAS needs two sets of RAM for VC* look-up tables on Ingress and Egress directions. Those RAMs are SSRAMs working at 50 MHz. The Reference Design for S/UNI-ATLAS is supported with enough SRAM for 16 k connections at the Ingress and Egress. The Egress uses one 128 k x 36 SRAM (36-bit wide data bus). The Ingress uses one bank of two 128 k x 36 SRAMs to make up the 72 bit wide data bus. The S/UNI-ATLAS must interface with synchronous flow-through SRAMs (non-pipelined). */ VC - Virtual Connection. This refers either to Virtual Path Connection (VPC) or Virtual Channel Connection (VCC) within a physical link.
10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
4.2.
DSLAM High-Speed LVDS Serial Interface The S/UNI-DUPLEX and S/UNI-VORTEX provide backplane interconnection through 100 to 200 Mb/s serial LVDS links. All cells flown to and from Core Card, and cells processed on the Core Card are concentrated on these high-speed links. Clock is not transmitted to avoid clock skew issues, and the receiver recovers the clock from the incoming data. For more information on the high-speed LVDS link, see DSLAM system design document [1]. 4.2.1. Example of LVDS Routing on Core Card
The Core Card provides an LVDS interface to both the LVDS-backplane and to the front panel. Block diagram, shown in Figure 5, highlights components that support LVDS on the Core Card. Figure 5. LVDS on Core Card
Jumper fields, manually settable
LEDs 1 LVDS Headers VORTEX 1 16 pairs 4 pairs LVDS
DUPLEX
LVDS
LVDS over cable
8 1 2 1 SSRAM DUPLEX 4 pairs
Clock 25MHz
S/UNI ATLAS
VORTEX 2
LVDS IEEE 1394 Connectors
LVDS
S/UNI-VORTEX 2
16 pairs
8 SDRAM LED Ejector Switch SDRAM
cPCI Bridge
Core Card
11 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PCI Bus over cPCI backplane
S/UNI APEX
SSRAM
SSRAM
J1
LVDS over LVDS-backplane
J5
SSRAM
S/UNI-VORTEX 1
16 pairs
SSRAM
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Manually settable header fields are used to direct LVDS flow. The setup must be done before the card is inserted into the DSLAM shelf. S/UNI-VORTEX-1 and the S/UNI-DUPLEX can provide an interface to J5 or to the front panel. S/UNI-VORTEX-2 provides an interface to the front panel only. The total number of LVDS traces to J5 (and running on the LVDS-backplane) is 40. This large number of high-speed connections may create crosstalk on the cPCI connector. Separating "hot" lines with ground pins can minimize this crosstalk. The LVDS traces to the front plate connectors are relatively long. Care must be taken to avoid crosstalk to/from digital lines. The front panel connectors are the FireWire type (IEEE 1394), designed to handle differential signals up to 400Mb/s. Other low cost solutions, such as UTP-5 RJ-45 type connectors, are physically too wide to support eighteen ports. 4.2.2. LVDS Transmitters vs. Hot Swap
The LVDS interface is fully hot swap compatible. The LVDS transmitters can stay active or can be turn off (disabled) on live cards, while another card is hot plugged in. For example, the transmitter disable function is executed on the S/UNI-DUPLEX by writing register 0x05 with value 0x30. The S/UNI-VORTEX registers 0x095, 0x0B5, 0x0D5, 0x0F5, 0x115, 0x135, 0x155 and 0x175 disable LVDS transmitter per HSS link by writing 0x08. After inserted card is operable, writing zero to appropriate bits in corresponding registers can activate the transmitters. IMPORTANT: Proper register write sequence is required to ensure cell transfer over the LVDS interface and Utopia bus. The sequence is implemented in the VORTEX Chipset driver files vcs_api1.c and dpx.c. It is important to make sure the S/UNI-DUPLEX OCAEN bit in register 0x0A stays disabled until S/UNIATLAS polling is enabled. The OCAEN is set to 1 at the very last write, enabling cell transfer from the S/UNI-DUPLEX at that interface. The above sequence applies to the card that is initialized after power up and also to any card that has interface setup changed. Software designers are required to observe sequencing in their drivers. More on LVDS can be found in sections 9.2, 9.3 and 10 in this document. 4.3. 8kHz Interface The S/UNI-DUPLEX and the S/UNI-VORTEX provide a mechanism for transporting an 8 kHz time stamp over the LVDS connection. This 8 kHz signal is
12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
used to synchronize the whole network with a single reference clock. Figure 6 shows an example of the 8 kHz DSLAM network synchronization.
Figure 6.
Example of 8kHz Clock Flow on Core Card
8kHz over ATM over LVDS Core Card-1
TX8K
Line Card-1 DUPLEX
8 kHz
WAN Card
8 kHz
TX8K RX8K
VORTEX
8 kHz
DUPLEX
DUPLEX
Line Card-2 DUPLEX
8 kHz
TX8K
VORTEX
CPLD (switch)
8 kHz PLL
8kHz over ATM over LVDS
Line Card-N
Header Connector
8 kHz
8 kHz
DUPLEX 8 kHz Reference
The 8 kHz signal is entered and received to/from the S/UNI-VORTEX or S/UNIDUPLEX at the dedicated pins TX8K or RX8K. The time reference is encoded in the third byte of the prepend attached to a modified ATM cell transmitted over the serial high-speed LVDS connection. A brief description of the circuit is as follows. The 8 kHz clock can be fed to the system at different points - through the Core Card, WAN Card, or Line Cards. The highlighted flow shows 8 kHz distributed from the Core Card. The 8 kHz time stamp is encoded in cells sent by the S/UNI-VORTEX and S/UNI-DUPLEX on the Core Card and then to the S/UNI-DUPLEX on the Line Card and WAN Card. The WAN Card filters out encoding jitter through the 8 kHz PLL, before it is used for further synchronization. The DSLAM Reference Design Line Card can derive 8 kHz time stamp and feed into the Comets. The Comet has an internal 8 kHz dejittering circuit; therefore, cards have no additional 8 kHz PLL. The Core Card 8 kHz path is controlled through the cPCI bridge and a CPLD.
13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The received 8 kHz clock on the S/UNI-VORTEX / S/UNI-DUPLEX pin RX8K is a pulse that lasts 16 clock cycles on the clock at the LVDS connection. If LVDS is at 200 MHz, then the pulse is 16 x 5 ns = 80 ns long and repeats at 125 us (8 kHz). Figure 7 shows an example of an oscilloscope captured time reference that has been recovered on the Core Card. Figure 7. A Example of Received 8 kHz Time Reference B
Graph A shows the edge of the 8 kHz reference clock inserted to the S/UNIVORTEX, received time reference pulse at the S/UNI-DUPLEX RX8K output pin, and resynchronized 8 kHz clock at the PLL output. Graph B shows jitter on the received time reference pulse and edge of the 8 kHz square wave at the PLL output. Attenuated edge jitter is approximately 19 ns, which can be converted to approximately 0.00015 UI peak-to-peak. For more information about the DSLAM 8 kHz clock distribution, see the DSLAM system design document [1]. Protection switching, executed in our lab, showed no adverse affect on the 8 kHz clock phase and frequency synchronization. For more information about network synchronization and phase-frequency shift, see the DSLAM system design document [1] and also in [9], [16], and [17].
14 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
5.
CORE CARD CHIPSET OVERVIEW This section briefly describes the DSLAM chipset.
5.1.
PM7324 S/UNI-ATLAS The S/UNI-ATLAS is the PMC-Sierra standard product that implements the following ATM Layer functions:
* * * *
OAM processing, according to the ITU-T I.610 1995 and 1998 living list. Header Translation on full VPI/VCI address range. Prepend and postpend tagging. Cell rate policing according to ITU-T I.371 using the Generic Cell Rate Algorithm. GFR Policing according to ATM Forum's Traffic Management 4.0 1998 living list. Per-PHY queuing to prevent head-of-line blocking.
*
*
The S/UNI-ATLAS performs both ingress and egress functionality. The ingress side has a SCI-PHY level 2 (Utopia L2) interface at the input, and a SCI-PHY level 1 (Utopia L1) interface at the output. Cells coming into the S/UNI-ATLAS from a PHY are identified according to the PHY ID, VPI, and VCI using a binary search process. The cells are processed according to the information stored in context RAM for the particular connection. Cells may also be copied to the microprocessor cell interface for external processing. The egress port has a SCI-PHY level 2 interface at both the input and output interface. The connection is identified (using a direct lookup process) by the PHY ID, VPI, and VCI, and processed according to the information in external RAM for the particular connection. Like the ingress port, cells can be copied to the microprocessor cell interface for external processing. The software, VORTEX Chipset Driver that controls the Reference Design Core Card, sets the cell header remapping in the S/UNI-ATLAS. The S/UNI-ATLAS is configured and controlled through a generic 16-bit asynchronous microprocessor bus. The S/UNI-ATLAS is implemented in low power 3.3 Volt CMOS technology. The microprocessor and JTAG interfaces are 5 Volt/ 3.3 Volt tolerant, while all other interfaces are 3.3 Volt only. The S/UNI-ATLAS is packaged in a 432-pin SBGA package.
15 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
For a more detailed description of the S/UNI-ATLAS, see the S/UNI-ATLAS Datasheet, PMC-971154 document [4]. 5.1.1. Ingress SRAM The Ingress VC Table is stored externally to the S/UNI-ATLAS in SRAM (Static RAM). The ingress SRAM data bus is 72 bits wide (8 bytes plus byte parity), with an address space of 20 bits (1 M). This creates enough context address space for 64 k VCs. The entire SRAM space does not have to be populatedr. If fewer than 64 k VCs are required or a subset of the S/UNI-ATLAS features are used, then the SRAM may be saved. The Ingress VC Table rows marked as 1011, 1100, 1101, and 1110 may be skipped. (In some isolated cases, mostly with older RAMs, glue logic may be required.) Figure 8 shows an example of a connection of a Synchronous SRAM 20-bit wide address interface on the S/UNI-ATLAS into a 256 k 17-bit wide address SRAM. This configuration allows 16 k of VC Tables. The figure also shows addressing structure of a VC Table. Figure 8.
ATLAS
19 17 16
S/UNI-ATLAS SRAM VC Table Addressing
Synchronous SRAM Interface
SRAM 256 k
Data Bus ISD[63:0] 63 0000 0001 0010 0011 0100
. .
Parity Bus ISP[7:0] 07 0
ISA[19:0] RAM Address Outputs
15 14 13
14 13
A[16:0] RAM Address Inputs
. 1100 1101 1110
TABLE 1 64x15
TABLE 2
0 0
TABLE 16,384 (16 k)
The four most significant bits in the ISA bus, ISA[16:19] must always be connected. Those bits point to a data row in the VC Table. The least significant portion of the address space can be used as required for each application. The above example uses 14 bits (ISA[13:0]) for the table address. The address space 14 in the example allows addressing for 2 (16 k) VC Tables. Bits 14 and 15 are unconnected.
16 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The total RAM space required for the above example is calculated as follows: (64 + 8) x 15 x 16384 = 17,694720 bits. Two 256 k 36-bit wide RAM devices allow storage of 262,144 x 36 x 2 = 18,874,368 bits. This is provided using one bank of two 256 k by 36 SSRAMs to make up the 72-bit wide data path. As there is only one bank of SSRAM, there is no address decode necessary. The Reference Design uses two GS88036T 256 k by 36 Synchronous SSRAMs manufactured by GSI Technology, Inc. A 100-pin TQFP package was chosen. Figure 9 shows the Ingress S/UNI-ATLAS to the SSRAM interface.
Figure 9.
ATLAS
VC Ingress S/UNI-ATLAS-SSRAM Connection
Synchronous SRAM Interface 4
GS84036T Synchronous 128 k by 36 SRAM #1 & #2
1 2 A[17:14] 4 A[13:0] A[13:0] 14 DQ[32:0] DQ[32:0] DQP[3:0] ISP[7:4] OEB GWB ADSCB CLK Vdd OEB GWB ADSCB CLK ADV LBO BWE ZZ FT ADSP BW[4-1] CE2 CE1 CE3 ADV LBO BWE ZZ FT Vdd
ISA[19:16] ISA[14:15] ISA[13:0] 14 64 ISD[63:0] 8 ISP[7:0] ISP[3:0] ISOEB ISRWB ISADSB ISYSCLK Vdd ISD[31:0]
A[17:14]
ISD[63:32]
DQP[3:0]
ADSP BW[4-1] CE2
CLOCK 50 MHz
CE1 CE3
For more information about how other configurations can be implemented, see the appendix in the S/UNI-ATLAS data sheet document, Interfacing SSRAM to the S/UNI-ATLAS. The appendix describes SSRAM configurations and several examples. The appendix also lists SSRAMs from various manufacturers that are compatible with the S/UNI-ATLAS and with this design in particular. For the S/UNI-ATLAS, synchronous flow-through (non-pipelined) SSRAMs must be used.
17 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
5.1.2.
Egress RAM
The Egress VC Table is stored external to the S/UNI-ATLAS in SSRAM. The addressing structure is similar to the ingress addressing shown in Figure 8. The egress SSRAM data bus is 36 bits wide (4 bytes plus byte parity), with an address space of 20 bits (1 M). This provides for 64 k connections, as with the Ingress VC Table. If fewer than 64 k connections are required or a subset of S/UNI-ATLAS features are used, then SRAM may be saved. The Core Card Reference Design has enough SRAM to support 16 k connections at the egress port. This is provided using one 256 k by 36 SRAM (1 MB). As there is only a single SSRAM, no address decode is necessary. For the S/UNI-ATLAS, synchronous flow-through, non-pipelined SSRAMs must be used. The Reference Design uses a GS88036B 256 k by 36 Synchronous SRAM manufactured by GSI Technology, Inc. (in a 100-pin TQFP package). Figure 10 shows the egress S/UNI-ATLAS - SSRAM interface. Figure 10. VC Egress S/UNI-ATLAS-SSRAM Connection
ATLAS GS88036T Synchronous 256 k by 36 SRAM
Synchronous SRAM Interface 4
ESA[19:16] ESA[14:15] ESA[13:0] 32 ESD[31:0] 4 ESP[3:0] 13
A[17:14]
A[13:0]
DQ[31:0]
DQP[3:0]
ESOEB ESRWB ESADSB ESYSCLK Vdd
OEB GWB ADSCB CLK ADSP BW[4-1] CE2 ADV LBO BWE ZZ FT Vdd
CLOCK 50 MHz
CE1 CE3
The four most significant bits in ESA bus, ESA[16:19] must always be connected.
18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
For more bus termination and signal integrity examples, see section 11 in this document. 5.2. S/UNI-APEX 5.2.1. Functional Description The PM7326 S/UNI APEX is a full duplex ATM traffic management device, that provides cell switching, per-VC queuing, traffic shaping, congestion management, and hierarchical scheduling for up to 2048 loop ports and up to four WAN ports. The S/UNI APEX provides per-VC queuing for 64K VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS. The S/UNI APEX provides three level hierarchical scheduling for port, COS, and VC level scheduling. There are two, three-level schedulers--one for the loop ports and one for the WAN ports. The three-level scheduler for the WAN ports provides: Weighted Interleaved Round Robin (WIRR) scheduling across the four WAN ports that enables bandwidth allocation selection between the ports. Priority Fair scheduling across the four COSs within each port. This class scheduler is a modified priority scheduler that allows minimum bandwidth allocations to lower priority classes within the port. Class scheduling within a port is independent of activity on all other ports. Three types of VC schedulers. VC scheduling within a class is independent of activity on all other classes Shaped fair queuing is available for four classes. If the COS is shaped, each VC within the class is scheduled for emission based on its VCs shaping rate. During class congestion, the VC scheduler may lower a VC rate in proportion to a normalization factor calculated as a function of the VC rate and the aggregate rate of all active VCs within the class. Weighted Interleaved Round Robin scheduling in which weights are used to provide fairness between the VCs within a class.
19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
-
-
-
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
-
Frame continuous scheduling where an entire packet is accumulated before it is transferred to a class queue.
The three-level scheduler for the loop ports provides weighted Interleaved Round Robin (WIRR) scheduling. This scheduling, across the 2048 loop ports, enables bandwidth allocation selection between the ports and ensures that minimal PHY layer FIFOing is required to support a wide range of port bandwidths. Supported port bandwidths are from 32 kb/s to 52 Mb/s. Priority scheduling across the four COSs within each port. Class scheduling within a port is independent of activity on all other ports.* VCs within a class are scheduled with a Round Robin scheduler or Frame Continuous scheduling. VC scheduling within a class is independent of activity on all other classes. Shaping is not supported on loop ports. The S/UNI APEX forwards cells through tail of queue enqueuing and head of queue dequeuing (emission), where tail of queue enqueuing is controlled by the VC context record and subject to congestion control, and head of queue dequeuing is controlled by the three level hierarchical schedulers. The VC context record allows for enqueuing to any queue associated with any port and supports full switching from a port to port. The S/UNI APEX supports up to 256 k cells of shared buffering in a 32-bit wide SDRAM. Memory protection is provided through an inband CRC on a cell by cell basis. Buffering is shared across direction, port, class, and VC levels. The congestion control mechanism provides guaranteed resources to all active VCs, allows sharing of available resources to VCs with excess bandwidth, and restricts buffer allocation on a per-VC, per-class, per-port, and per-direction basis. The congestion control mechanism supports PPD and EPD on a CLP0 and CLP1 basis across per-VC, per-class, per-port, and per-direction structures. EFCI marking is supported on a per-VC basis. Congestion thresholds and packet awareness is selectable for each connection. The S/UNI APEX provides flexible capabilities for signaling, management, and control traffic. Four independent uP receive queues exist where both cell and AAL5 frame traffic may be enqueued for termination by the uP. A staging buffer is also provided enabling the uP to enqueue both the cell and AAL5 frame traffic to any outgoing queue. AAL5 SAR assistance is provided for AAL5 frame traffic to and from the uP. AAL5 SAR assistance includes the generation and checking of the 32-bit CRC field and the ability to reassemble all the cells from a frame in the VC queue before placement on the uP queues. Any or all of the 64 k VCs may be configured to be routed to/from the uP port. Any or all of the VCs configured to be routed to/from the uP port may also be configured for AAL5 SAR assistance
20 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
simultaneously. OAM cells may be routed optionally (per-VC selectable) to a uP receive queue or switched with the user traffic. CRC10 generation and checking is optionally provided on OAM cells to and from the uP. The S/UNI APEX maintains cell counts of CLP0 and CLP1 cell transmits on a per-VC basis. Global CLP0 and CLP1 congestion discards are also maintained. Various error monitoring conditions and statistics are accumulated or flagged. The uP has access to both the internal S/UNI APEX registers and the context memory, as well as diagnostic access to the cell buffer memory. The S/UNI APEX provides a 16-bit wide Any-PHY compliant loop side master/slave interface that supports up to 2048 ports. Egress cell transfers across the interface are identified through an inband port identifier prepended to the cell. To accept the cell, the slave devices must match the inband port identifier with their own port ID or port ID range. Per port egress flow control is executed through a 12-bit address polling bus to which the appropriate slave devices respond with out-of-band per port flow control status. Ingress cell transfers across the interface is executed through a combination of UTOPIA L2 flow control polling and device selection for up to 32 slave devices. The Any-PHY loop side interface may be reconfigured as a standard single port 16-bit wide Any-PHY or UTOPIA L2 compliant slave interface. The 16-bit prepends are supported optionally on both ingress and egress for cell flow identification, enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The S/UNI APEX provides an 8- or 16-bit Any-PHY or UTOPIA L2 compliant WAN side master interface that supports up to four ports. The 16-bit prepends are supported optionally on both ingress and egress for cell flow identification, enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The S/UNI APEX provides a 32-bit microprocessor bus interface for signaling, control, cell, and frame message extraction and insertion, VC Class and port context access, control and status monitoring, and configuration of the IC. Microprocessor burst access is supported for registers, cell and frame traffic.. The S/UNI APEX provides a 36-bit SSRAM interface for context storage that supports up to 4 MB of context for up to 64 k VCs and up to 256 k cell buffer pointer storage. Context Memory protection is provided with 2 bits of parity over each 34-bit word. The total number of cells, the total number of VCs, support for address mapping, and shaped fair queuing is limited to the amount of context and cell buffer
21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
memory available. Table 1 shows the most common combinations of memory and features. TABLE 1.
Context Memory Size ZBT SSRAM 1 MB 2 MB 2 MB 4 MB
Feature Set as a Function of Memory Capacity
Cell Buffer Memory Size SDRAM 4 MB 4 MB 4 MB 16 MB 16 k 16 k 64 k 64 k 64 k 64 k 64 k 256 k # VC # Cell Buffers Address Mapping Support Yes Yes No Yes Shaping Support No Yes No Yes
NOTE: The table may not correspond to the final settings on the Core Card due to RAM availability and other reasons. Designers should follow the RAM size recommendations outlined in the above table and in the calculations presented in document [12]. The Reference Design Core Card supports the layout for 4 MB of Context Memory SSRAM and 16 MB of Cell Buffer SDRAM, thus allowing 64 k of VCs and 256 k of buffered cells. The maximum RAM size was chosen for evaluation purposes and interface verification. However, due to RAM availability, the Core Card may be populated with smaller size NBT RAM. Board inspection is required to determine actual RAM size. The RAM interfaces are described in following sections. The S/UNI-APEX provides facilities to enable sparing capability with another S/UNI-APEX device. The facilities enable a warm standby capability, in which connection setup between the two devices can be maintained identically but some cell loss occurs at the point of device swapping. The facilities do not include a cell-by-cell lock step between the two S/UNI-APEX devices. To avoid any cell replication, queues in the spare S/UNI-APEX are kept empty, causing all queued traffic in the active S/UNI-APEX to be lost at the point of switch over. Since connection setup is maintained identically between the two S/UNI-APEX devices, switch over can happen instantaneously allowing you to avoid connection timeout or teardown issues. The S/UNI-APEX facilities provided are the disable and filter control bits in the Receive and Transmit Control register. These control bits are asserted in the spare S/UNI-APEX to ensure the queues remain empty until swapping is initiated. Alternatively, asserting only the Filter enable bits allow signaling and control traffic continuity to be maintained to the spare S/UNI-APEX. This enables
22 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
datapath integrity testing on the spare plane and ensures control communications paths to the spare plane are usable. 5.2.2. Context Memory SSRAM Interface
The S/UNI-APEX context memory SSRAM interface can be configured for two types of synchronous RAMs: Late Write or Zero Bus TurnaroundTM (also known as NBT). The Core Card is assembled with a pipelined ZBT/NBT SSRAM. Schematic and board layout support optional placement of a RAM, up to 2 Mbytes each with address lines CMA<19..0> connected. Also, the layout supports the RAM core supply at 2.5 V for GS8162Z18 (the pinout is preliminary at the time this document is created, and pinout verification is advised). The GS162Z18 option requires zero-ohm resistor that strap 2.5 V to the CORE1 rail. Other RAMs from Samsung and possibly from IDT and Cypress may be placed with minimum rework on the board. Schematic and layout, of the Core Card Reference Design Issue. 3, supports only GSI GS882Z18 NBT RAM without any strapping. RAMs are set in a single bank that consist of two 512 M x 18 ZBT SRAMs (1 MByte each) and provide 2 MB of SSRAM memory. The SSRAM bus is clocked at 80 MHz. Signal integrity simulation and timing simulation was done to derive design guidelines. Serial termination resistors are inserted in data path to attenuate backreflections and improve signal integrity. For more examples on bus termination and signal integrity, see Section 11, Bus Termination Examples, in this document. The S/UNI-APEX SSRAM address bus CMA[19:0] is connected with all lines that allow an address up to 1,048,576 (1 M). CMCEB is used to control chip selection on RAMs. The data bus CMD[33:0] is split into lower and upper chunks and connected to respective SSRAM devices. Each 17-bit wide segment is associated with a parity bit CMP[0] or CMP[1], which are connected to the corresponding DQ[17:0] 18-bit wide ports on the SSRAM devices. The S/UNI-APEX generates the parity bit , which is stored into RAM. The OE# inputs on the SSRAM is tied to ground. The read/write line CMRWB determines if the data bus is in a read or write cycle. For more information about bus timing, see Section 11, Bus Termination Examples, in this document. If the S/UNI-APEX detects a parity error, the two parity bits protecting the 34-bit data bus can trigger an interrupt at the S/UNI-APEX. Parity check generation can be used to detect data corruption in highly reliable data transfer protocols or networks.
23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 11 shows the S/UNI-APEX to the SSRAM interface.
Figure 11.
Dual Bank Configuration for ZBT SSRAM
Synchronous ZBT SRAM Interface
APEX
CMAB[18:17] CMA[19] CMA[18:0] CMD[33:17] CMD[16:0] CMP[1:0]
GS882Z18 512x18 ZBT SSRAM #1 and #2
1 VDDQ VDD A[19] 3.3V 2 VDDQ VDD A[19] A[18:0] DQ[17:0] DQ[16:0] 3.3V 3.3V or 2.5 V
19
A[18:0]
2
DQ[17]
DQ[17]
CMRWB SYSCLK 3.3V CMCEB
W# CK CE2 CE1# CE3# ADV/LD# B#[b:a] OE# 3.3V
W# CK CE2 CE1# CE3# ADV/LD# B#[b:a]
FT
FT
CLOCK 80MHz
ZZ CKE#
ZZ OE# CKE#
For examples of a generic interface to SSRAM, see the S/UNI-APEX data sheet. The Core Card schematic Issue 3 on page 9 shows an optional core supply with 2.5 V for larger NBT SSRAMs. The board is laid out with a copper cutout underneath the RAMs, allowing a 3.3 V or 2.5 V supply with different resistors placement on assembly line. The Core Card printed circuit board Rev. 3 is assembled with a 3.3 V version of NBT SSRAM. The designer should evaluate the availability of RAMs, and possibly choose to eliminate the 2.5 V supply by shorting the copper cutout to 3.3 V. 5.2.3. Cell Buffer SDRAM Interface The Reference Design shows the S/UNI-APEX with 16 MB of SDRAM for queued cell buffering. The SDRAM buffer consists of a single bank with two RAMs for a 32-bit wide data path that provides room for up to 64 k cells. The SDRAMs are Micron's MT48LC4M16A2TG 8 MB (size derived from 1 Mb x 16 x 4 banks = 64 kb = 8 MB).
24 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The S/UNI-APEX allows CRC-16 check on the first 60 bytes in per-cell basis of the data from the SDRAM. If an error occurs, an interrupt is sent to the microprocessor. Figure 12 shows an example of a 16 MB SDRAM. Figure 12.
APEX
CBA[11:0] 16 CBDQ[16:0] CBDQ[31:17] CBCSB CBRASB CBCASB CBWEB CBBS[0] CBBS[1] CBDQM[0] CBDQM[1] CKE SYSCLK CLK Vdd CLK 16
Single Bank SDRAM 4 MB for 64 k Cells
SDRAM Interface 12 A[11:0] DQ[15:0] DQ[15:0] CS# RAS# CAS# WE# BA0 BA1 DQML DQMH CS# RAS# CAS# WE# BA0 BA1
MT48LC4M16A2 SDRAM 8 MB = 64 Mb = 1Mb x 4 banks x 16 bits
1 A[11:0] 2
DQML DQMH CKE Vdd
CLOCK 80MHz
The data mask signals CBDQM[1:0] at the S/UNI-APEX control the read/write cycle on the CBDQ[31:0] bus. The S/UNI-APEX and SDRAMs run at 80 MHz for the Core Card. Bus termination and signal integrity examples are shown in this document in Section 11, Bus Termination Examples, 5.3. S/UNI-VORTEX The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial backplane interconnect architecture. Multiple S/UNI-VORTEX devices can reside on a common cell processing card beside a traffic management device. The traffic management device exchanges
25 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
cells with the S/UNI-VORTEX through a 16-bit wide SCI-PHY or Any-PHY interfaces (bus). The flow control is affected across this interface through cell available signals that the S/UNI-VORTEX generates. In the downstream direction, the traffic management device can poll for the availability of a buffer for each logical channel. In the upstream direction, an indication is provided whether one or more cells are queued in the S/UNI-VORTEX for transfer. Each S/UNI-VORTEX can be connected to eight Line Cards through high-speed 100 to 200 Mb/s serial links. Each upstream link has its own queue. If a queue becomes nearly full, a flow control indication is sent downstream. In the downstream direction, each logical channel has a dedicated cell buffer to avoid head of line blocking. The serialization of cells from the cell buffers is throttled by flow control information sent from the line card through the upstream high-speed link. A microprocessor port provides access to internal configuration and monitoring registers. That port can also be used to insert and extract cells in support of a control channel. LVDS INTERFACES, BOTH DIRECTIONS:
*
Eight independent four-wire LVDS serial transceivers, each operating at up to 200 Mbps across PCB or backplane traces or across up to 10 meters of four-wire twisted pair cabling for inter-shelf communications. Usable bandwidth (excludes system overhead) of 186 Mbps, for each direction of each LVDS link. Fully integrated LVDS clock synthesis and recovery. No external analog components are required.
*
*
RECEIVE DIRECTION:
*
Weighted round-robin multiplex of cell streams from the eight LVDS links into a single cell stream that is transferred to the parallel bus under control of the bus master. LVDS link and S/UNI-VORTEX identifiers that are added to each cell (along with the PHY identifier already added by S/UNI-DUPLEX) for use by the ATM layer to identify the cell source. Back-pressure that is sent to the far end to prevent an overflow of the receiver FIFO.
*
*
TRANSMIT DIRECTION
*
Per-PHY and microprocessor port back-pressure that are used on each of the eight links to prevent the overflow of downstream buffers.
26 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
*
Device polling that provides Utopia-like TCA status for 264 PHYs (includes 8 control channels), based on back-pressure from the LVDS links. Cell transfer, where the bus master adds a PHY address to each cell through a 12-bit identifier. The S/UNI-VORTEX decodes and accepts the cells for its links, based on software-configured base addresses.
*
PARALLEL BUS INTERFACE:
* *
Both directions: 16-bit wide, 50 MHz maximum clock rate, bus slave. Cells transferred to the bus - Utopia L2 compatible with optional expanded length cells. The cell appears as from a single PHY, with a cell prepend that identifies the source PHY ID of each cell. Alternatively, Utopia L2 compliance is supported by placing the PHY ID inside the UDF/HEC fields of a standard ATM cell. Cells received from the bus. The Any-PHY bus is similar to Utopia L2, however with optional expanded length cells and expanded addressing capabilities. The S/UNI-VORTEX appears to the bus master as a 264port, multi-PHY device (eight links, each with 32 PHYs & a communication channel). The PHY address is added as the cell prepend or optionally in the HEC/UDF field when standard length cells are desired.
*
Example of a 16-bit wide UTOPIA L2 cell is shown below. Utopia L2 Cell
Bit0
CLP
VPI/VCI example: VPI = 100 (0x64), VCI = 32 (0x20)
PAYLOAD48 PAYLOAD2 PAYLOAD4 0000 0100 00000110 1 BINARY 2 00000010 2 0x02 0000 0x0 0x0 HEX PAYLOAD47 PAYLOAD1 PAYLOAD3 4 5 27
27
VCI
PT ADDRESS[13:0] VCI
Bit8
Bit7
Bit15
1
2
3
Core Card software driver applications sets UL2 bus to have word 3 overwritten with logical channel ID from S/UNI-VORTEX and phy ID from S/UNI-DUPLEX.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
0x06 1
VCI
VPI
0x4
VPI
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
MICROPROCESSOR INTERFACE
* * *
8-bit data bus, 8-bit address bus. Provides read/write access to all configuration and status registers. Provides CRC32 calculation and cell transfer registers to support an embedded microprocessor-to-microprocessor communication channel over the LVDS link.
5.4.
S/UNI-DUPLEX The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used for traffic concentration within a DSLAM. The device is ATM specific. It exchanges contiguous 53 byte cells with PHY devices. The PHY interface can be either clocked serial data or SCI-PHY/Any-PHY. A clocked serial data configuration of up to sixteen channels is supported. Cell alignment is established through HCS (Header Check Sequence) delineation. 43 The cell payload is scrambled and descrambled with a x + 1 polynomial. Rate adaptation is performed through idle cell insertion and extraction. Each PHY interface has a dedicated four-cell FIFO in both upstream and downstream directions. All cell streams are multiplexed into a high-speed serial stream. Each S/UNIDUPLEX can connect to two 100 to 200 Mb/s Low Voltage Differential Signal (LVDS) serial links. The internal transmit clock is synthesized from a lower frequency reference run at 1/8 of the line rate. An extended cell format provides four extra bytes for the encoding of flow control, timing reference, PHY identification, and link maintenance information. A redundant link is provided to allow connection to two cell processing cards. A microprocessor port provides access to internal configuration and monitoring registers. The port may also be used to insert and extract cells in support of a control channel. The S/UNI-DUPLEX is typically used with its sister device, the S/UNI-VORTEX, to implement a point-to-point serial backplane interconnect architecture. For more information about S/UNI-DUPLEX, see the S/UNI-DUPLEX Datasheet.
28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
5.5.
CPCI Bridge This section briefly introduces the cPCI bridge functionality. 5.5.1. PCI9054 PCI Bridge
To interface the VORTEX chipset residing in the Core Card to the host CPU residing in slot 1 of the cPCI shelf, a PCI-to-Local-bus bridging device is required. The device chosen for this Reference Design is the PLX PCI9054 PCI Bus Master I/O Accelerator Chip. Some features that were deciding factors in becoming the bridge of choice for this Reference Design are:
*
PCI v2.2 compliant 32-bit 33 MHz Bus Master Interface Controller that enables PCI Burst Transfers up to 132 Mbytes/second General Purpose Bus Master Interface featuring an advanced Data Pipe ArchitectureTM which includes two DMA engines, programmable Target and Initiator data transfer modes and PCI messaging functions PCI v2.2 Power Management Spec compatible Flexible +3.3 V, +5 V Tolerant Local Bus operation up to 50 MHz 32-bit multiplexed, or non-multiplexed local bus supporting 8-, 16-, and 32-bit peripheral and memory devices CompactPCI hot-swap capability
*
* * *
*
Since the S/UNI-APEX requires a multiplexed bus, for this Reference Design, the PCI 9054 bridge is programmed to perform in a 32-bit multiplexed mode (J mode). The fact that the S/UNI-APEX is a 32-bit device, the S/UNI-ATLAS is a 16-bit device, and the S/UNI-VORTEX and S/UNI-DUPLEX are both 8-bit devices adds complexity to the local bus, on which they all reside. While the local bus can support 8-, 16-, and 32-bit devices, for this Reference Design, the PCI 9054 operates solely in 32-bit mode. (For more information, see section 8.4.) 5.5.2. SEEP Basics
The PCI 9054 provides a serial EEPROM (SEEP) port for loading configuration information on power-up and reset. The SEEP is programmed with address space boundaries for the VORTEX chipset and the Core Card IDs. The CPLD is used with the PCI9054 to provide address decoding and microprocessor port control for the DSLAM chips being accessed from the PCI bus. For more information about SEEP, see sections 8.6 and 8.7. Examples of data reading on reset are shown in section 16 APPENDIX C: EXAMPLE OF SEEP READING ON RESET in this document.
29 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
6. 6.1.
SIGNAL FLOW ON THE CORE CARD IN BRIEF Upstream Direction The following process refers to the VORTEX Chipset Driver defaults or test routines, for example, the cells on Utopia L2 into the S/UNI-ATLAS Ingress are 27 words with the ID written into the HEC/UDF word. Cells that originate from a Comet or PHY device on the Line Cards and are destined for the WAN Card are manipulated in the following manner:
*
Upstream cells are received by the PHY and buffered until the S/UNIDUPLEX reads them. As a cell is read from the PHY, the S/UNI-DUPLEX writes the originator PHYID[4:0]--or microprocessor ID, in the case of the embedded Inband Communication Channel (ICC)--into the LVDS data structure and sends the cell through the LVDS serial link to its corresponding S/UNI-VORTEX on both the active and stand-by Core Cards. The S/UNI-VORTEX receives cells by servicing its eight links in a simple weighted round-robin fashion. As the S/UNI-VORTEX reads cells from the high-speed serial link, it inserts into the HEC/UDF field the ADDR[13:0], which contains its own hardwired S/UNI-VORTEX ID VADR[4:0] (ADDR[13:9]), the high speed LINKID[2:0] (ADDR[8:6]), and the logical channel ADDR[5:0]. At this point, cells are available to the Scy-PHY/UL2 bus that connects the S/UNI-VORTEX to the S/UNI-ATLAS. (software test routines generate cells which are Utopia L2 compatible.) After an upstream cell is read in by the S/UNI-ATLAS, it will use the PHYID, LINKID, and VORTEX IDs to perform a lookup function that results in a short connection (or switch) tag being inserted into the HEC/UDF before passing it to the S/UNI-APEX. The S/UNI-APEX uses the tag to directly address the context and control information pertaining to the cell. The present test routines (supplementing VORTEX Chipset Driver) translate the header in the S/UNI-ATLAS. The S/UNI-APEX provides per-VC congestion control, buffering, and queuing, and provides switching and traffic shaping into four high-speed WAN up-link ports. Upstream traffic is passed from the S/UNI-APEX back through the S/UNI-ATLAS Egress. The S/UNI-ATLAS first provides counting and OAM functionality. Then the S/UNI-ATLAS transfers the data onto the Core Card's S/UNI DUPLEX to transmit over the LVDS serial link onto the WAN Card.
*
*
*
30 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
*
The S/UNI-DUPLEX on the Core Card first writes the destination PHY ID (3:0) (or EIC) into all cells. Then the S/UNI-DUPLEX transmits them to the S/UNI DUPLEX that resides on the WAN Card. The upstream traffic received by the WAN Card's S/UNI-DUPLEX is passed onto the card's S/UNI-QJET, which frames the data into DS3 format and sends it out over the appropriate (one of four) DS3 link.
6.2.
Downstream Direction The following process refers to the software driver defaults or test routines, for example, the cells on Utopia L2 into S/UNI-ATLAS Ingress are 27 words with the ID written into the HEC/UDF word. Cells that originate from the WAN and are destined for a Line Card or PHY device are manipulated in the following manner:
*
Data received by the WAN Card's four DS3 links is passed to the S/UNIQJET which multiplexes the data, and sends it to the WAN Card's S/UNIDUPLEX for transmission to the Core Card over the high-speed serial link. The WAN Card's S/UNI-DUPLEX writes the originator PHY ID (3:0) into the LVDS data structure before transmitting data to the CORE card. Downstream data received by the Core Card's S/UNI-DUPLEX is passed to the S/UNI-ATLAS. The cells proceed through the S/UNI-ATLAS and onto the S/UNI-APEX, where all ATM layer functions are performed on the cells. The S/UNI-APEX appends to all PHY-destined cells a unique 12-bit address that identifies the destination S/UNI-VORTEX, LINK, and PHY IDs (or S/UNI-VORTEX, LINK, and the EIC). The data is then placed on the ANY-PHY bus that connects the S/UNI-VORTEX devices to the ATM layer of the DSLAM shelf. The present test routines (supplementing Chipset Driver) translate header in the S/UNI-ATLAS. The 12-bit address is used by the S/UNI-VORTEX devices that are connected to the ANY-PHY bus to determine whether or not a cell placed on the bus is destined for them; if they are, then the cell should be read. Downstream cells received by the S/UNI-VORTEXes are stripped of the prepended address segment. The S/UNI-VORTEX writes the destination PHY ID into the LVDS data structure and sends cells across the appropriate LVDS serial link (7:0) to the corresponding S/UNI-DUPLEX device that resides on the Line Card. The Line Card's S/UNI-DUPLEX device, after receiving cells from the high-speed serial interface, strips the prepended bytes from the cells and sends the data to the appropriate PHY (or to the microprocessor in the case of the ICC).
31 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
*
*
*
*
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
7.
HOT SWAP The Core Card has been designed to be hot-swap compatible. The Hot Swap Specification [19] states: "The basic purpose of the Hot Swap addition to CompactPCI is to allow the orderly insertion and extraction of boards without adversely affecting system operation."
7.1.
cPCI and Power Rail Hot Swap The Core Card uses a hot-swap compatible cPCI bridge, PLX PCI9054, and a hot-swap controller, the Linear Technology LTC1654. The cPCI connector is assembled with three different length pins, as required by the Hot Swap Specification [19]. The supporting circuitry is also carefully designed to not impair the hot-swap ability. Figure 13 shows an example of the hot-swap circuit. Figure 13.
Backplane
Medium length pins
Example of a Hot-Swap Circuit
R200 0.01 R30 0.01 Q3
+3.3 V
Q2
+3.3 Vin +5 Vin Early +5V
R222
5.0 V
5 V SEN1 Q4 R1 ON
3.3 V SEN2 GATE 1 GATE 2
Charge Pump
LTC1645
GND Shortest
BD_SEL#
R223 Q1 R52 Op-Amp
100 k 5.0 V +3.3 V L_RSTB 1.0 V RN84
LTC1326
Voltage Sensor and RESET#
R256
Reset RSTB
PCI_RST# Early VI/O
cPCI Bus
PCI_RST# VI/O (+5 V)
+3.3 V1
n x 15 k
3.3V
3 k
SW1
n x 15 k
PCI 9054
LEDin/LEDon
ENUM# GND Longest
100 k
ENUM#
200 Blue LED
Ejector handle 1 k
HEALTHY#
HEALTHY# and PCI9054 reset Circuit
PCI9054_RSTB
32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The above figure shows that the card is about to be placed into the shelf. The first three mating pins are: the longest GND (ground), the longest +5V (if cPCI is +5 V environment), and long VI/O. The longest +5V pin is also called early 5 V. In a 3.3 V environment, it is referred to as early 3.3 V. The early VI/O polarizes some of the cPCI bus pins with +5V through 15 kohm resistors. The early +5V flows into a network of resistors and transistors. The current is limited to few mA. The Op-Amp, biased with the resistive divider R52/R256, provides about 1.0 V of the precharging voltage to the selected cPCI bus interface lines through n x 15 kohm resistors. Immediately after the early +5 V and GND pins are connected, the current flows through resistors R222 and R223, forcing transistor Q1 to saturate and hold the ON pin on LTC1645 at low. That activity keeps the GATE1 and GATE2 pins on the swap controller at low voltage and in turn keeps both MOSFET transistors opened (off). Card insertion proceeds, and some milliseconds later, the medium length pins on the J1 connector (most of the pins) mate with the cPCI backplane. The +5 Vin line connects to: Vcc on LTC1645, and transistors Q2 and Q3 (through R30 and R200). When the card is pushed deep into the connector, finally the shortest pin (BD_SEL#) connects ground to the node with resistors R222 and R223. That activity turns off Q1 and allows the ON pin to go high. The LTC1645 starts internal timer, and at the same time starts ramp voltage at the GATE1/2 pins. After about 50 ms, the GATE1/2 voltage turns on transistors Q30 and Q200 gradually, limiting the inrush current. Eventually, GATE1/2 goes above 12 V (controlled with internal pump charge) and turns transistors Q30 and Q200 completely on. The reset and voltage supervising device LTC1326 senses +5 V and 3.3 V going above the predefined threshold, triggering the internal timer, which sets RSTB high after about 200 ms. The LTC1326 device also allows two additional control lines triggering reset at the RSTB line. One of the lines is connected through a resistor to the cPCI reset line PCI_RST#. The other line is connected to the PCI9054 reset output, allowing for software reset on the local bus. At this point, the +3.3 V is supplied to the PCI9054 cPCI bridge. The PCI9054 sets ENUM# (open drain active low) signaling to the host CPU, indicating that a new card is inserted. The ENUM# line stays low until the host processor toggles the bit in the internal register at the PCI9054 bridge. If the ejector handle is fully closed and the microswitch is activated, and if the host card RESET (PCI_RST#) is activated and released, the ENUM# line goes from low to high.
33 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
If the "PCI_RST#" is asserted (held low) by the host processor card (while the card is inserted or at any time), then the LTC1326 keeps RSTB asserted. Optionally, the PCI_RST# can be connected through a 100 kohm resistor to the base of the P-channel transistor Q4. If the PCI_RST# is asserted, then the Q4 turns on and forces the current through a resistor and the base of transistor Q1. This keeps Q1 saturated, and the LTC1645 via both MOSFETs cuts off +5 V and 3.3 V to the card. If the card is already powered, the assertion of the PCI_RST# turns off transistors Q30 and Q200 and cuts off supply voltage to the rest of the circuit - a sort of a very hard reset. NOTE: the serial 0.01 ohm resistor and copper traces in +3.3 V path gives over 35 mV drop at sensing pins at LTC1645. That may create hypersensitivity to small glitches, as the threshold level on sensing pins on LTC1645 is about 50 mV. Designers should observe voltage drop and adjust resistor value to have sensing voltage less than 1/2 of the threshold (or add RC filtering elements). If LTC1645 on the Core Card triggers too often, then resistor can be temporary shorted. The toggling switch SW1 through the front panel ejector handle initiates the card removing software sequence. The PCI9054 sets ENUM# to low and informs the host CPU that the card is about to be removed. The blue LED remains turned off (dark) until the host CPU confirms it is safe to remove the card; at this point, the blue LED is turned on. The supply voltage removal is a reversed action of the insertion with the very first pin (BD_RST#) disconnected. That action forces Q1 to saturate and the ON pin to go low. The GATE1/2 voltages are turned off. In turn, transistors Q30 and Q200 are off as well. The turn-off ramps are uncontrolled and abrupt. An accidentally toggled ejector handle may trigger software action. If the ejector handle is returned to its operating position, the system may detect it and start the boot-up procedure, as if the card had just been inserted. NOTE: Hot-swap action requires software, which is not supported with this release of the Reference Design board level driver. Also, the host processor card must support the detection of ENUM# activity for the software hot swap. 7.2. LVDS Hot Swap The LVDS interface is fully hot swap compatible. Proper register write sequence is required to ensure cell transfer on the LVDS and Utopia bus. The sequence is implemented in the VORTEX Chipset driver files vcs_api1.c and dpx.c. The most important is to make sure the OCAEN bit in register 0x0A stays disabled until S/UNI-ATLAS polling is enabled. The OCAEN is set to 1 in the as the very last
34 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
write, allowing cell transfer from the S/UNI-DUPLEX at that interface. Software designers are required to observe sequencing in their drivers. 7.3. Blue LED and Microswitch Control The LEDON/LEDIN, pin 53 on PCI9054 (LED_SWITCH\I), is continuously sampled to detect the position of the microswitch. Figure 14 shows the sampling signal. Figure 14. LED_SWITCH\I Line Siganl
A
B
Graphs A and B show a sampling signal output by PCI9054 pin53 LEDON/LEDIN (schematic signal LED_SWITCH\I), captured at TP115 (R233). The microswitch must be in a position where the 3 kohm pull-up resistor (R243), is connected to the LED_SWITCH\I line. Internal to PCI9054 capacitor is charged with that resistor, making time constant of about 200 ns - derived from graph "B" above. The internal capacitor can be calculated at about 60 pF. If resistor is disconnected, the sampling pulses disappear.
35 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8. 8.1.
CPCI INTERFACE, PCI BRIDGE AND CPLD Control Interface Block Diagram Figure 15 shows the block diagram for the cPCI and local bus microprocessor interface on all chips. Figure 15.
cPCI
Serial EEPROM
cPCI and Local Bus Microprocessor Interface
CPLD
AD[31:0] A[28:2]
CS AD[31:0]
APEX
P P control
L_A[13:2]
L_A[18:14] L_AD[15:0]
A[11:0] D[15:0]
PCI9054
PCI_AD[31:0] PCI_control
L_AD[7:0] CS[4:0] L_A[11:2]
VX_DX_D[7:0] CS
ATLAS
P P control
VX_DX_A[9:0] A[9:0] D[7:0]
Control
Control
P interface control
VORTEX-1
CS P P control
J1
A[9:0] D[7:0] Blue LED LEDs CS
Hot Swap
VORTEX-2
P
P control
A[7:0] D[7:0]
DUPLEX
P CS P control
The 32-bit multiplexed PCI_AD[31:0] ADRESS/DATA bus connects through 10 ohm resistors from the J1 connector to the PLX PCI9054 bridge. The PCI side of the PCI9054 is described in the data book (the PCI interface is beyond the scope of this document). Throughout the Core Card test procedures, problems relating to the PCI interface were not experienced. Proper layout and component soldering assured flawless access to the cPCI bus. Some problems were related
36 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
to the size of the SEEP, which must be 4 kbit (for example, NM93CS66). Also, the VORTEX Chipset Driver must match the data stored in the SEEP, must read registers on each chip properly, and verify chip revision. As of July 2000, the chipset revision is as follows: S/UNI-DUPLEX rev. B, S/UNI-VORTEX rev. B, S/UNI-APEX rev. B, and S/UNI-ATLAS rev. D. Designer should check if available devices have other revision numbers. The local bus side is described as follows. The bridge is set to Multiplexed Bus Mode, as required by the S/UNI-APEX, which operates only with a multiplexed bus (address and data on the same bus). The remaining devices have the microprocessor interface option to work in both the multiplexed and non multiplexed modes. For this Reference Design, those devices operate in nonmultiplexed modes. Part of the Core Card board address and data are run through the CPLD, allowing a more balanced load on the local bus LAD[31:0]. The LAD[31:0] bus connects directly from the PCI9054 to the S/UNI-APEX microprocessor address/data port. Bits LAD[15:0] connect also to CPLD and to the S/UNI-ATLAS microprocessor data port. On the S/UNI-VORTEX1, S/UNIVORTEX2, and S/UNI-DUPLEX, bits LAD[7:0] are routed to the data ports through the CPLD. A direct connection from the PCI 9054 to the local devices creates uneven loads and trace lengths for different bus lines--with the highest capacitance load and the longest traces on lines LAD[7:0] (all devices), and the lowest at LAD[31:16] (S/UNI-APEX only). For this reason, lines LAD[7..0] are routed through the CPLD. Also, proper resistive termination placed along the bus lines helps with signal integrity, as shown later in this document. Signal integrity issues, such as, edge distortion and overshoot, can corrupt data and/or prevent the bus from operating at the maximum speed. The PCI9054 has an additional dedicated address bus LA[28:2] that allows chip select CS[4:0] to be stable during data cycles and during burst read/writes (no address latch needed). The LA[28:2] bus is split in two sections: lower LA[13:2] for register address and higher LA_SEL[4:0] for chip select. The LA[13:2] is routed directly to the S/UNI-ATLAS microprocessor address port and to the CPLD. The CPLD connects some of those lines to the S/UNI-DUPLEX and S/UNI-VORTEX microprocessor address ports. The LA[28:2] address does not include the least significant two bits. Those two bits are used as byte indicators when accessing an 8-bit wide address. For 32-bit addresses, all addresses are expected to be long-word aligned, making the least significant two bits always 00. More on local bus is shown in section 8.4. The CPLD receives data and address lines from the PCI9054,not only for buffering purposes, but also for reading and writing of the CPLDs internal registers. The CPLD also provides additional control lines to and from all DSLAM chips.
37 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8.2.
PCI Bridge - CPLD Interface The PCI9054, with the CPLD, have the job of providing an interface to five VORTEX chipset devices that reside on the Core Card, and to the host processor card that reside at slot 1 of the cPCI shelf. The VORTEX chipset connects to the local bus for which the PCI9054 is the Bus Master. The microprocessor ports of each devices are partially fed by the CPLD. The other portions of the microprocessor interfaces are fed directly from the PCI9054, for example, the address and data at S/UNI-APEX and S/UNI-ATLAS. The CPLD receives all local control signals from the PCI9054 and the address lines required for device decoding. The CPLD is programmed to provide all necessary functions to the DSLAM devices' microprocessor ports. These functions include chip select, read data, write data, interrupt, and burst for those devices that support bursting -(in this Reference Design, only the S/UNI-APEX). The host processor card initiated transfer is serviced by the PCI 9054, which receives instructions and passes the control signals and address/data lines to the CPLD. The CPLD decodes the address and supplies the correct control signals to the DSLAM device being accessed.
8.3.
Major Control Lines Between S/UNI-APEX, CPLD and PCI9054 Interface The PCI9054 provides address/data bus, local address bus, and a set of control lines on the local side. The CPLD plays a key role in creating proper signaling on the multiplexed bus. Figure 16 shows the address, data buses and control lines for the S/UNI-APEX and other devices.
38 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 16.
S/UNI-APEX, CPLD, and the Local Bus Microprocessor Interface
L_AD[31:0] L_A[13:2] L_AD[15:0]
L_AD[31:0] L_A[13:2] L_A[18:14]
AX_ADS AX_CSB AX_WR
L_BHOLD L_DENB L_LWR/RB L_BLASTB L_ADSB L_READYB
APEX
AX_BURSTB AX_BLASTB
PCI9054
AX_READYB AX_BTRMB AX_WRDNB AX_INTHIB AX_INTLOB
L_BTERMB
L_INTB L_RSTB L_SERRB L_WAITB
CPLD
L_AD[15:0] L_A[13:2]
X X X
L_BIGEND L_BREQO L_SERRB L_BE2 L_BE3 L_DMPAF L_BREQI L_CCS L_DMPAF L_USERI L_USERO L_MODE1 L_MODE2 L_TEST
ATLAS
X X X
VORTEX-1
X X X
VORTEX-2
X X X
DUPLEX
X X
The block diagram shows the detailed connections to the S/UNI-APEX and general connections to other devices. The PCI9054 provides numerous control lines. The active signals, L_HOLD, L_DENB, L_LWR/RB, L_BLASTB, and L_ADSB are connected to the CPLD. Two additional lines L_SERRB and
39 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
L_WEITB are also connected but not used for the CPLD logic. CPLD outputs three control lines: L_READYB, L_BTERMB, and L_INTB terminated at the PCI9054 bridge. The L_INTB line is a combined interrupt from all devices. The AX_BURSTB line is connected from CPLD to the S/UNI-APEX, and it is always asserted when accessing the S/UNI-APEX. Other control lines are not used and may have pull-up or pull-down resistors. For more information about S/UNI-ATLAS, S/UNI-VORTEX, and S/UNI-DUPLEX interfaces, see the schematics. Examples of the signal timing are shown in section 17 APPENDIX D: LOCAL BUS TIMING EXAMPLES in this document. 8.4. Address Mapping In the Reference Design, there is a local bus on which a 32-bit device (S/UNIAPEX), a 16-bit device (S/UNI-ATLAS), and 8-bit devices (S/UNI-DUPLEX and S/UNI-VORTEX) reside. This constraint provides two possibilities:
*
To use the 9054 ability to provide a dynamic interface to a 32-bit PCI bus to 8-, 16-, and 32-bit local busses. While this option would have maximized memory efficiency on the CPU side, it also would have increased the design's complexity, in both hardware and software. To treat all devices as if they were 32 bit devices (the option chosen for this Reference Design). The CPU assigns a 32-bit address space to all devices. For 8-bit devices, 24 bits of every CPU word are ignored. For the 16-bit device, half of all CPU words are ignored. The major fault with this design choice is the waste of CPU memory. However, because the DSLAM chipset does not require a large amount of memory space, this design choice is acceptable, given that it reduces the design's complexity.
*
Address translation works as follows. For a 32-bit local bus, the PCI9054 expects all addresses to be word (32-bit) aligned, causing all addresses to end with 00. As a result, the PCI9054 does not even provide the lowest two address bits on the local address bus (LA<28:2>). To accommodate this, every local address is mapped to a word-aligned boundary on the CPU side, that is, register 0011b on the S/UNI-DUPLEX is addressed as 1100b on the CPU side. Because the third S/UNI-DUPLEX register is mapped to the twelfth CPU register, several CPU registers are unused. This corresponds to the ignored bits mentioned in the previous paragraph. The same register on the local bus is derived in hex as 0x03 * 4 = 0x0C and with the offset specific to this Reference Design, it becomes the S/UNI-DUPLEX address 0x1400C.
40 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8.5.
PLX PCI9054 Address Spaces The PCI9054 offers three separate local address spaces, which can be programmed individually to offer 8-, 16-, or 32-bit accesses, burst capability, wait states, etc. If this design had used different local bus widths for the different designs, all three-address spaces would have been necessary. The threeaddress spaces are not necessary because all the devices are treated as 32-bit devices. For this Reference Design, a one-address space is used for all devices.
8.6.
Card ID Number The Card ID number stored in the SEEP may change with the progress of the programming work. It is recommended to remove SEEP, and place in a programmer and read content. TABLE 2 shows application-specific Card ID numbers, stored in the SEEP.
TABLE 2.
SEEP Version
Preliminary*
DSLAM PCI Card ID Codes
00h 02h Vendor ID
5056h
44h Subsystem ID
000Dh
46h Subsystem Vendor ID
5056h
Device
-
Device ID
0022h
SP
Unconfigured PLX 9054
9054h
10B5h PLX
2350h DSLAM Core Card Kit
11F8h PMC-Sierra
*/ Some Core Cards may have preliminary SEEP load. Also, the SP version has the Class Code set to 0x0600, for a PCI bridge.
The present version of ID load is described as follows. The 10B5 hex is the PLX registered vendor ID. The 11F8 hex is the PMC-Sierra registered vendor ID. Subsystem ID 2350 hex is unregistered ID for the Core Card Kit. 8.7. Serial EEPROM Load Registers The PLX 9054 can be initialized to a large extent by reading the data from its serial EEPROM (SEEP) port during initialization. Reading the data from the SEEP is equivalent to directly writing to the 9054 configuration registers through the CPU.
41 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The DSLAM Reference Design Core Card includes a SEEP for this purpose. Table 3 shows the SEEP Load Registers' contents. TABLE 3.
SEEP Offset 0h 2h 4h 6h 8h Ah Ch Eh 10h 12h 14h 16h 18h Device ID Vendor ID Class Code Class Code / Revision Maximum Latency / Minimum Grant Interrupt Pin / Interrupt Line Routing MSW of Mailbox 0 LSW of Mailbox 0 MSW of Mailbox 1 LSW of Mailbox 1 MSW of Range for PCI to Local Address Space 0 LSW of Range for PCI to Local Address Space 0 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 1Ah LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0 1Ch 1Eh 20h 22h MSW of Mode/DMA Arbitration Register LSW of Mode/DMA Arbitration Register MSW of EPROM write Protected Area LSW of Local Miscellaneous Control Register / LSW of Local Bus Big/Little Endian Descriptor Register 24h 26h 28h MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM 2Ah LSW of Local Base Address (Remap) for PCI-to-Local Expansion ROM 2Ch MSW of Bus Region Descriptors for PCI-to-Local Bus Accesses 2Eh LSW of Bus Region Descriptors for PCI-to-Local Bus Accesses (including local bus width - 32) LBRD0[15:0] 0043h LBRD0[31:16] 4200h EROMBA[15:0] 0000h EROMRR[31:16] EROMRR[15:0] EROMBA[31:16] 0000h 0000h 0000h MARBR[31:16] MARBR[15:0] PROT_AREA [15:0] LMISC[7:0] / BIGEND[7:0] 0100h 0000h 0030h 0500h LAS0BA[15:0] 0001h Description
PLX 9054 Serial EPROM Load Registers
PLX 9054 Register Bits Affected PCIIDR[31:16] PCIIDR[15:0] PCICCR[23:8] PCICCR[7:0] / PCIREV[7..0] PCIMLR[7:0] / PCIMGR[7:0] PCIIPR[7:0] / PCIILR[7:0] MBOX0[31:16] MBOX0[15:0] MBOX1[31:16] MBOX1[15:0] LAS0RR[31:16] LAS0RR[15:0] LAS0BA[31:16] 9054h 10B5h 0600h 0000h 0000h 0100h 0000h 0000h 0000h 0000h FFFEh 0000h 0000h Setting
42 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
SEEP Offset 30h 32h 34h
Description
PLX 9054 Register Bits Affected
Setting
MSW of Range for Direct Master-to-PCI LSW of Range for Direct Master-to-PCI MSW of Local Base Address for Direct Master-to-PCI Memory
DMRR[31:16] DMRR[15:0] DMLBAM[31:16]
0000h 0000h 0000h
36h
LSW of Local Base Address for Direct Master-to-PCI Memory
DMLBAM[15:0]
0000h
38h
MSW of Local Bus Address for Direct Master-to-PCI I/O Configuration
DMLBAI[31:16]
0000h
3Ah
LSW of Local Bus Address for Direct Master-to-PCI I/O Configuration
DMLBAI[15:0]
0000h
3Ch
MSW of PCI Base Address (Remap) for Direct Master-toPCI
DMPBAM[31:16]
0000h
3Eh
LSW of PCI Base Address (Remap) for Direct Master-toPCI
DMPBAM[15:0]
0000h
40h
MSW of PCI Configuration Address register for Direct Master-to PCI I/O Configuration
DMCFGA[31:16]
0000h
42h
LSW of PCI Configuration Address register for Direct Master-to PCI I/O Configuration
DMCFGA[15:0]
0000h
44h 46h 48h 4Ah 4Ch
Subsystem ID Subsystem Vendor ID MSW of Range for PCI to Local Address Space 1 LSW of Range for PCI to Local Address Space 1 MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
PCISID[15:0] PCISVID[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS1BA[31:16]
2350h 11F8h FFFEh 0000h 0000h
4Eh
LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
LAS1BA[15:0]
0000h
50h
MSW of Bus Region Descriptors (Space 1) for PCI -toLocal Accesses
LBRD1[31:16]
0000h
52h
LSW of Bus Region Descriptors (Space 1) for PCI -toLocal Accesses
LBRD1[15:0]
0040h
54h 56h
MSW of Hot Swap Control LSW of Hot Swap Control / Hot Swap Next Capability Pointer
Reserved HS_NEXT[7:0] / HS_CNTL[7:0]
0000h 4C00h
58h - 100h
Blank
-
FFFFh
43 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
An example of the source code for the SEEP. (NM93CS66) is shown below. The bold characters are entries from the above table. The fields 58h to 100h are not highlighted to make it easily readable (those fields are all FFFFh).
:020000020000FC :10000000905410B506000000000001000000000027 :1000100000000000FFFE00000000000101000000E1 :100020000030050000000000000000004200004316 :1000300000000000000000000000000000000000C0 :1000400000000000235011F80000000000000000FD :100050000000004000004C00FFFFFFFFFFFFFFFF1C :10006000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA0 :10007000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF90 :10008000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80 :10009000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF70 :1000A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF60 :1000B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF50 :1000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40 :1000D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF30 :1000E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF20 :1000F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF10 :10010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF :10011000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF :10012000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDF :10013000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFCF :10014000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF :10015000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFAF :10016000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9F :10017000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8F :10018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F :10019000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6F :1001A000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5F :1001B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4F :1001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F :1001D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF2F :1001E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF1F :1001F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0F :00000001FF
8.8.
CPLD The CPLD is used for address decoding and load balancing on the local bus, 8 kHz clock routing, LED control latches, and interrupt logic. The interrupts from each device can be presented to the host CPU on a single read cycle, speeding up interrupt servicing.
44 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8.8.1.
Local Bus Memory Map
TABLE 4 shows the local bus memory map. TABLE 4.
ADDRESS [16..0] 0x00000 - 0x00A00 0x04000 - 0x04008 0x08000 - 0x0A000 0x0C000 - 0x0C804 0x10000 - 0x10804 0x14000 - 0x1420C
Local Bus Memory Map
Description S/UNI-APEX registers CPLD registers for interrupts, LEDs and 8 kHz routing (offset 0x4000) S/UNI-ATLAS registers (offset 0x8000) S/UNI-VORTEX-1 registers (offset 0xC000) S/UNI-VORTEX-2 registers (offset 0x10000) S/UNI-DUPLEX registers (offset 0x14000)
Address range for the S/UNI-APEX is 0xA00 as per datasheets. Multiplying register numbers by 4 and adding offset derives address range for all other devices. The address range per each device is the highest specified in the corresponding data sheets for the present chip revisions. Example: S/UNI-VORTEX highest register 0x201 * 4 = 0x804, with offset 0xC804; S/UNI-ATLAS, highest register 0x800 * 4 = 0x2000, with offset 0xA000. DSLAM software driver prevents accessing address that is higher than specified in the data sheets per each chip. Chip select is done with the PCI9054 address LA[16..14], which are bundled with a couple of more bits into LA_SEL<4:0> (as shown on the schematic on page 12). For the above devices, the address ports (registers address) on the devices are wired to the address bus using bits LA<13..2> (directly or through the CPLD). The two least significant bits are ignored, due to a 32-bit long word of four bytes on the address and data bus. Address mapping is necessary to treat all local devices as 32-bit devices on the PCI side. (See section 8.4.) Address to each device is incremented by one bit, with bits LA_SEL[2:0] on the chip address bus. The CPLD registers 0x04000, 0x4004 and 0x04008 support interrupts, LEDs, and 8 kHz routing. Reprogramming is possible, depending on the designer's needs. The DSLAM chipset has assigned memory space of up to 0x14FFC (decimal 86012).
45 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8.8.2.
CPLD Registers
This section briefly describes CPLD registers. Each register is 16-bit wide. TABLE 5.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R
Interrupt Register 0x4000
Function Reserved Reserved S/UNI-DUPLEX INT Enable S/UNI-VORTEX-2 INT Enable S/UNI-VORTEX-1 INT Enable S/UNI-ATLAS INT Enable S/UNI-APEX INTLO Enable S/UNI-APEX INTHI Enable Reserved Reserved S/UNI-DUPLEX INT S/UNI-VORTEX-2 INT S/UNI-VORTEX-1 INT S/UNI-ATLAS INT S/UNI-APEX INTLO S/UNI-APEX INTHI Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 8 through 13 can be set to logic 1, enabling the corresponding interrupt. If enabled, then any active interrupt from the VORTEX chipset pulls low the interrupt output pin on the CPLD, which is connected to pin LINTB on the PCI9054. Bits 0 through 5 are set to logic 1 asynchronously by interrupt lines from each device. NOTE: The CPU sets bits 8-13. The CPLD logic sets bits 0-5 (based on connected VORTEX chipset interrupt lines) allowing a single read from the CPLD to determine device interrupt.
46 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Example of possible LED assignment is shown in TABLE 6 below. TABLE 6.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
LED Register 0x4004
Function Reserved Reserved Operating Mode - Status LED (yellow) Reset and microprocessor interface (red) S/UNI-VORTEX-1 LCD S/UNI-VORTEX-1 LCD S/UNI-VORTEX-1 LOS S/UNI-VORTEX-1 LOS S/UNI-VORTEX-2 LCD S/UNI-VORTEX-2 LCD S/UNI-VORTEX-2 LOS S/UNI-VORTEX-2 LOS S/UNI-DUPLEX Port-2 LCD S/UNI-DUPLEX Port-2 LOS S/UNI-DUPLEX Port-1 LCD S/UNI-DUPLEX Port-1 LOS Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED D7 WAN LED D6 Line 9-16 LED D5 Line 1-8 LED D4 Status Notes
Bits 0 through 11 set red LEDs on the front panel for loss of signal (LOS) or loss of cell delineation (LCD) on the corresponding LVDS receivers. Alarms have to be detected by the host processor through interrupts and written to the CPLD register 0x4004. If the Core Card is in operating mode, bit 13 may be written 1/0 at about two times per second. If the Core Card is in stand-by mode, bit 13 may be 1 and Status LED is lit steadily. If the Core Card is malfunctioning, bit 13 is 0 and LED is turned off. NOTE: VORTEX Chipset Driver does not have the alarm LED control implemented. Also, on reset, the internal CPLD programming turns on all LEDs to for visual inspection, and later, the software script should turn the LEDs off. Check LED behavior for programming. Designer may program LEDs as needed.
47 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
TABLE 7.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
8 kHz Routing Register 0x4008
Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Clock to PLL [1] Clock to PLL [0] PLL output to all TX8K Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 0 = 0. All 8 kHz inputs TX8K on S/UNI-VORTEX-1, S/UNI-VORTEX-2, and S/UNI-DUPLEX are fed from the J65 header 8 kHz input. No PLL in the signal path. Bit 0 = 1. All 8 kHz inputs TX8K on S/UNI-VORTEX-1, S/UNI-VORTEX-2, and S/UNI-DUPLEX are fed from the 8 kHz PLL. The source of the signal to the PLL input is determined with bits 1 and 2. Bit-1 = 0 and bit-2 = 0. Clock to PLL from the S/UNI-DUPLEX pin RX8K Bit-1 = 1 and bit-2 = 0. Clock to PLL from the S/UNI-VORTEX-1 pin RX8K Bit-1 = 0 and bit-2 = 1. Clock to PLL from the S/UNI-VORTEX-2 pin RX8K Bit-1 = 1 and bit-2 = 1, reserved. The 8 kHz output header J72 is fed with 8 kHz from J65 if Bit0 = 0 or from PLL output if Bit0 = 1.
48 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Notes on Register Bits: 1. Writing values into unused register bits has no effect. To ensure software compatibility with future versions of the product, unused register bits should be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero, therefore, unused register bits should be masked off by the software when they are read. All configuration bits that can be written into can also be read back. This allows the processor that controls the Core Card to determine the programming state of the block. Writeable register bits are cleared to logic zero on reset, unless otherwise noted. Writing into read-only normal mode register bit locations does not affect the CPLD operation, unless otherwise noted. Alarms And Interrupts
2.
3. 4. 8.8.3.
Interrupts from each device are fed into the CPLD, and are derived by the host processor card through the cPCI bridge INTA# line. The interrupt-causing device can be determined by a single read of the CPLD register instead of five reads from the DSLAM chipset. Alarms can be read directly from devices also. 8.8.4. 8 kHz Channel
Figure 6 shows how the CPLD supports routing of the 8 kHz signal to and from any port. 8.8.5. Address Decoding and Chip Enable
The CPLD supports dynamic (no latching) address decoding and generation of chip enable signals. Those signals are routed to each chip individually. 8.8.6. CPLD Type
The CPLD used in this Reference Design is the Xilinx XC95288 with 288 microcells (registers). The data bus width is 32 bits for the S/UNI-APEX, 16 bits for the S/UNI-ATLAS and CPLD, and 8 bits for the S/UNI-VORTEX and S/UNIDUPLEX. For a preliminary VHDL source code for the CPLD, see Section 0.
49 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
8.9.
CPLD Block Diagram Figure 17 shows the CPLD block diagram. Figure 17. CPLD Block Diagram
la<18..14> (address decoder) l_adsb l_wr_rb la<20..2> l_ad la<11..2>
Dx Vx Block
Address Decode & Logic
csb_dx csb_vx1 csb_vx2 dx_vx_rdb dx_vx_wrb intb_dx intb_vx1 intb_vx2 vx_dx_d<7..0> vx_dx-a<9..0>
Latch
AS Block
Address Decode & Logic
l_readyb Logic csb_as as_rdb as_wrb as_busyb intb_as
AX Block
csb_ax ax_adsb ax_wr ax_blastb intb_axhi intb_axlo ax_burstb ax_btermb ax_readyb ax_wrdoneb
l_blastb
Address Decode & Logic
l_bhold l_btermb
Register Block
Address Decode & Logic
TCK TDI TDO TMS
l_denb l_waitb l_lserrb optional leds optional controls unused I/O
INT Register LED Register 8KHz Register
Logic
l_intb LEDs
In-circuit programming header
dxrx_8k vx1rx_8k vx2rx_8k ck_8kref ck_pll_out l_clk rstb
50
ck_pll_in ck_8kout ck_8kout_all
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
9. 9.1.
CONNECTORS ON CORE CARD CPCI Connectors 9.1.1. J1 on Core Card
The J1 connector, that mates with P1 on the 3U high cPCI backplane, provides power to the Core Card. The connector provides the PCI bus interface, which is connected to the PCI9054 bridge. The J1 connector has to provide the hot-swap capability. The connector senses the staggered pins on insertion and removal of the Core Card from the DSLAMshelf. The serial MOSFET transistors control the power rails. Connector J1 follows the pinout recommendation found in documents [18] and [19]. 9.1.2. J2, J3, and J4 on Core Card
The J2, J3, and J4, the cPCI-scheme connectors, are not populated on the Core Card. The J3 connector on a card that is placed into the DSLAM development shelf may collide with a metal rail that runs across the LVDS-backplane. 9.1.3. J5 on Core Card
System Design document [1] shows the J5 pinout. The J5 connector terminates LVDS from the S/UNI-VORTEX-1 and S/UNIDUPLEX. Those ports provide an interface to the WAN and Line Cards through the LVDS-backplane. NOTE: All connectors that mate with the backplane follow the cPCI backplane scheme. The Core Card uses J1 and J5 connectors only. The J2, J3, and J4 names are retired to avoid confusion and to bring uniform connector naming. 9.2. LVDS Interface on the LVDS-backlane The LVDS interface to the LVDS-backplane is provided through the J5 connector exclusively. The Core Card mates with the custom LVDS-backplane at slot 5 and slot 6.
51 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
9.3.
LVDS Interface on the Front Panel The LVDS interface on the front panel is provided through the IEEE 1394 FireWire connectors. Total of eighteen connectors with AC coupling allows access to high-speed ports at S/UNI-VORTEX-1, S/UNI-VORTEX-2 and S/UNIDUPLEX. See section 10 LVDS INTERFACE for more information.
9.4.
CPLD Programming Interface on J34 The CPLD programming interface is provided through the J36 header connector. For more information about connections, see the schematics on page 13 Additional Xilinx programming cable with a programming head is required for downloading code into the CPLD. The programming software can be downloaded from the Xilinx web site WARNING: Take caution while handling cables and maintaining boards. Most interfaces may not have ESD discharge protection.
9.5.
25 MHz Output on J45 The recovered clock on the high speed LVDS is divided by eight, and it is output at the S/UNI-DUPLEX pin E11 RCLK (at TTL level). The J45 connector is for test purposes only.
9.6.
RESET Header J64 The J64 header allows hardware reset to all VORTEX chipset devices (excluding PCI9054). For normal operation a shunt must be placed on pins 1 and 2. When the strap is placed on J64 pins 2 and 3, the RSTB local reset line to is asserted. That also forces HEALTHY# pin high.
9.7.
8 kHz Interface on J65 and J72 The 8 kHz interface on the Core Card is accessible on the board only. Header connectors are provided, with J65 for 50 ohm TTL level input and J72 for TTL level output (+3.3 V CMOS logic equivalent). Figure 18 shows the 8 kHz interface Core Card.
52 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 18.
8 kHz In
8 kHz Interface
1 k 56 75
J65
Rload
CPLD
Core Card
8 kHz Out
56
74
J72
9.8.
JTAG Interface on J66 The JTAG interface on the Core Card is accessible on the board through the header connector J66. The JTAG daisy-chain is connected for the VORTEX chipset only. The JTAG interface is provided but not tested. For more information about the connections, see the schematics on page 12.
9.9.
Mictor Connectors J70 and J71 The purpose of the J70 and J71 high density Mictor connectors is to allow board troubleshooting and CPLD development. The connectors are optional and may not be populated on all boards.
9.10. Clock Control Header J73 The J73 header must be open for normal operation. This header shuts down 25 MHz local bus clock. Do the strapping with the global reset on J64, while the CPLD is being programmed. Make sure the strap is removed after programming. (The Core Card doesn't misbehave during CPLD programming, even with the local bus 25 MHz clock running and without the RSTB asserted.) 9.11. Optional Reset to CPLD Header J74 The purpose of J74 is disconnecting the optional global reset to CPLD. The header is not populated.
53 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
9.12. Ejector Handle Switch Header TP115 Molex header TP115 allows the connection of the ejector micro-switch cable with the board and PCI9054. The microswitch toggles when the front panel ejector changes position, and notifies the PCI9054 and the host CPU about the status change. 9.13. Miscellaneous Test Points The Core Card allows the placement of additional headers on multiple test points, that are distributed throughout the board. Those headers may not be populated. NOTE: the TWRENB line is wrongly labeled as TPRTY. See schematic page 8. The TPRTY is at TP86.
54 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
10.
LVDS INTERFACE The connector pinout and interface circuit is briefed in this section. All connectors that mate with the backplane follow the cPCI backplane population option -- J1, J2, J3, J4, and J5. The Core Card uses J1 and J5 connectors only. The LVDS interface to the custom LVDS-backplane is provided exclusively through connector J5. The Core Card mates with the custom LVDS-backplane at slot 5 and slot 6.
10.1. LVDS Front Panel Interface The IEEE 1394 cable is wired with pins swapped on each end. This type of wiring requires matching pinouts on the Core Card and the Line/WAN Card. Figure 19 shows the LVDS connector pinout on the DSLAM cards. Figure 19. LVDS Pinout on DSLAM Cards Line/WAN Card Core Card
Shield and ground TX 1 3 2 4 5 6 Jumper Field Board Connector IEEE 1394 Cable 5 1 3 2 4 6 Jumper Field TX
LVDS
RX
LVDS
RX
Board Connector IEEE 1394
1 Connector pinout - front view 3 5
2 4 6
The pinout is functional only. The physical interface has serial capacitors 1.0 uF (or 0.22 uF) on input and output. Inputs are biased with the resistive divider and
55 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
line termination. Capacitors are permanently soldered without the bypass option. The Line and WAN Cards have transformer coupling, which can be modified for capacitor coupling through de-soldering only. Jumper fields allow for a front panel or backplane interface. The total count of the LVDS interfaces on the Core Card is eighteen. The total count of connectors occupies the entire front panel, preventing placement of other connectors (like 8 kHz stratum clock). The S/UNI-VORTEX-1 port P[0] through P[7] and S/UNI-DUPLEX port P1 and P2 can be wired to the front panel and to the LVDS-backplane through the Jumper Field. The S/UNI-VORTEX-2 port P[0] through P[7] are wired to the front panel only. The LVDS copper lines routing was shown earlier in Figure 5. Figure 20 shows the LVDS header straps. Figure 20. LVDS Header Straps Core Card S/UNIVORTEX 1
Front Back
P0
P7
S/UNIDUPLEX
P1 P2 Jumper Field for S/UNI-DUPLEX
Jumper Field for S/UNI-VORTEX 1 Back Front
A total of 40 shunts are needed for all LVDS ports. Headers and shunts are on a 2 mm grid. ESD Protection on LVDS Ports The LVDS is inherently unprotected for ESD with capacitor coupling on the Core Card interface. The Line and WAN Cards may have transformer coupling that withstand ESD discharge. Take caution when handling cables and maintaining boards.
56 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
10.2. LVDS Eye Pattern at Jumper Field Tests We have investigated LVDS signal integrity, and the results are presented below. The eye pattern on the transmitted LVDS signal is captured with the TEK TDS784 oscilloscope in differential mode. The signal was connected with two setups. The first one used high frequency probes, and the second one used short 50 ohm cables. Figure 21 shows the test results. Figure 21. Wave Shapes with a Single Active LVDS Transmitter
A
B
C ore C a rd U nd er T es t TX+
CH1 D U P LE X CH2
C ore C ard U nd er T est
C1 D U P LE X C2
TX+ TX-
C H 1, 50 ohm C H 2, 50 ohm T ek T D S 784A DSO
TX100 ohm
T ek P 6245 T ek T D S 784A P robes DSO
Graph A shows S/UNI-DUPLEX LVDS transmitting the waveform at the header connector, measured with high frequency oscilloscope probes. The waveform is terminated with the 100 ohm resistor, and the signal is probed with Tek P6245, <1 pF, 1 Mohm, 1.5 GHz probes.
Graph B shows the waveform obtained by direct connection with 50 ohm coaxial cables into 50 ohm oscilloscope inputs. Serial capacitors must be inserted, because direct termination into 50 ohm to ground overloads the transmitter and corrupts the LVDS signal. Both cases use the differential math function CH1- Ch2.
57 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Signal integrity measured with oscilloscope probes is inappropriate for this application. The signal shows excessive waves or back reflections, which may lead to a false conclusion about signal quality. The correct measurement is to terminate the signal directly into the oscilloscope using short coaxial cables and AC coupling. Transmitted data pattern is of random type with very low baseline wander, as needed for signal integrity tests. The waveforms look different with transformer coupling, as implemented for the Line Card and WAN Card. 10.3. LVDS Eye Pattern over LVDS-Backplane Tests The LVDS interface to the custom LVDS-backplane is provided exclusively through connector J5. The Core Card mates with the LVDS-backplane at slot 5 and slot 6. In the LVDS backplane test, the Core Card is placed into the DSLAM test shelf with the LVDS-backplane, and eye pattern is measured at the header on the Core Card and then on the WAN Card. The Core Card is placed at slot 5 and the WAN Card at slot 8. Figure 22 shows the total length of trace, which is about 35.5 cm or 14 inches.
58 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 22.
LVDS Over Backplane Test Connections
7.5 c m 3 inch es
L V D S -b ackp lan e Z -P ack Z -P ack
17.8 cm 7 inches
10 cm 4 inches
O scilloscope
H eader H eader
RX+
RX-
TX+
TXLV D S R eceiver
C H 1 , 5 0 oh m C H 2 , 5 0 oh m
LVDS T ran sm itter
C o re C ard
W A N C ard
The signal goes through two header connectors and two Z-pack, 2 mm cPCI connectors, before it is connected with a short 50 ohm coaxial cable into the 50 ohm oscilloscope inputs. AC coupling is maintained with serial capacitors. Figure 23 shows eye patterns at the transmitter header and at the receiver header. Figure 23. LVDS at Core Card and Line Card with LVDS backplane
B - signal at RX header
A - signal at TX header
The LVDS-backplane attenuates the LVDS signal from 675 mV to 640 mV, which results in 0.5 dB (or 5 %) amplitude attenuation. Some near-edge distortions are
59 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
amplified and are more visible after running the signal over the backplane. The overall signal is of a very good quality and allows easy reclocking. A possible reason for back reflections is a small miscalculation of the differential pair impedance. The board was designed with 50 ohm per trace, as it would be a single line. Due to the coupling effect, the virtual impedance of the pair is changed and is not 100 ohm any more. Also, the differential pair goes into two coax cables, creating additional impedance discontinuity. The measurement techniques need further evaluation.
NOTE: Double AC termination on the LVDS path may cause baseline wander if not designed properly. Excessive baseline wander together with long cables may cause bit errors. Designers may investigate solution with AC coupling on one card only, or use large capacitor coupling - about 1 uF. Also, metallic loopback executed for test and troubleshooting is very susceptible to double AC coupling and may cause misleading data corruption. With metallic loopback the LVDS data goes four times through AC coupling aggregating baseline wander problem.
60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
11.
BUS TERMINATION EXAMPLES This section briefly describes the bus termination method on various buses that are present on the Core Card. Proper digital line termination is critical for signal integrity and timing. Termination may prevent data corruption caused by a large signal overshoot. The overshoot may create current flow into silicone and internal silicone crosstalk, which is very difficult to detect. See document [5] for more on signal integrity.
11.1. Microprocessor Bus Termination Figure 24 shows the local microprocessor bus termination. Figure 24. Microprocessor Bus Termiantion
Microprocessor local Bus at 25 MHz L_AD<31..0> Board
APEX
50 mm 2" 56 Rs1
L_AD<31..16> 56 TP88 63 mm Rs2 2.5 "
90 mm 3.5 " L_AD<15..0> 30 mm 1.2 "
ATLAS PCI9054 CPLD
The measurements, done on the Core Card board Rev. 1, show a very large overshoot on the signal edges. After reviewing termination options, it was determined that placing the termination resistor, Rs1, at the L_AD<15..0> bus joint towards the longest branch at the S/UNI-ATLAS was optimal. Placement was based on signal integrity simulation and verified through a test. The second resistor, Rs2, was already placed next to the PCI9054 and is optional. The upper half, L_AD<31..16>, connects between PCI9054 and S/UNI-APEX only, and it has the Rs2 termination. The termination Rs1 placement at the central T-joint of
61 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
the bus is due to the bi-directional nature of the bus, where any device can drive the digital line. Figure 25 shows examples of the bus signal. Figure 25. A Examples of Signal Integrity on uP Bus B
Figure A shows the bus signal without termination resistors. Figure B shows the bus signal, L_AD<0>, measured on TP88 with the termination resistors distributed as presented in Figure 24 earlier. Signal overshoot reaches over one volt on both the positive and negative edges on the non-terminated bus. Serial termination resistors completely eliminate the overshoot. It is strongly recommend to have proper termination resistors on the microprocessor bus. It is common practice to terminate the Utopia, Scy-PHY, and RAM buses and to leave the microprocessor bus non-terminated. Usually, the microprocessor bus is physically the largest one on the board, reaching throughout all major components on the PCB. With edges in the nanosecond range, back reflections can reach well above clamping diode range, causing the uncontrolled current flow into silicone. We observed in our lab that a significant overshoot causes data corruption that was very difficult to troubleshoot. In the worst case scenario, board redesign with serial termination resistors, is the only solution.
62 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
11.2. Downstream Any-PHY Bus Termination Figure 26 shows the Any-PHY bus termination. Figure 26. Any-PHY Bus Termiantion
Board
APEX
VORTEX 2
VORTEX 1
38 mm 1.5 "
110 mm 4.2 "
38 mm 1.5 "
Rs1
56
LTDAT<15..0>, LTADR<11..0>, LTENB, LTPA, LTPRTY, LTSX
Any-PHY Bus at 50 MHz CPLD PCI9054
ATLAS
Signal simulation, done prior to the board layout, helped to find the best position for the termination resistor. Simulation pointed to T-joint as the optimal placement for the resistor. Both directions of data flow have the same T-joint termination placement. Figure 27 (below) shows an example of signal integrity on LTDAT<0> at the S/UNI-VORTEX-1.
63 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 27.
Example of Signal Integrity Downstream at VORTEX-1
The timing shows about 5.2 ns margin on hold time, while writing data to the S/UNI-VORTEX-1 on Any-PHY bus.
11.3. Upstream/Downstream UL2 Bus Termination Figure 28 shows the upstream/downstream UL2 bus termination with the S/UNIVORTEX1, S/UNI-VORETEX2, S/UNI-DUPLEX, and S/UNI-ATLAS.
64 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 28.
Upstream/Downstream UL2 Bus Termination
Board
APEX
VORTEX 2
DUPLEX 45 mm 1.8 "
VORTEX 1
45 mm 1.8 " RDAT<15.00>, RADDR<4..0>, RPRTY, RRDENB, RCA, RSOC Rs1 56 50 mm 2"
45 mm 1.8 "
UL2 Bus at 50 MHz CPLD PCI9054
ATLAS
The signal simulation shows T-joint as the optimal placement for the serial termination resistor. The simulation was done before board layout. Both directions of the data flow have the same T-joint termination placement. The best solution for the split trace length is to keep it symmetrical. In this case, the branches are at about 45 mm (or 1.8 inch) each. Figure 29 shows an example of signal integrity on LTDAT<0> at the S/UNIVORTEX-1.
65 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 29.
Example of Signal Integrity Upstream at VORTEX-1
The timing shows about 5.2 ns margin on hold time on RDENB. Also, the appropriate timing margin exists on the RADDR<0>. This is the SCY-Phy/UL2 bus at the S/UNI-VORTEX-1. 11.4. S/UNI-APEX - S/UNI-ATLAS Bus Termination Figure 30 shows the UL1 and UL2 buses, between the S/UNI-ATLAS and S/UNIAPEX, that are terminated with serial resistors.
66 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 30.
S/UNI-APEX - S/UNI-ATLAS Bus Termiantion
Board
APEX
140 mm 5.5 "
165 mm 6.5 "
VORTEX 2
DUPLEX
VORTEX 1
Rs1 56
WRDAT<15..0>, WRENB, WRPA, WRPRTY, WRSOP Rs1 56
WTDAT<15..0>, WTADR<2..0>, WTENB, WTPA, WTPRTY, WTSOP
CPLD PCI9054
UL1 and UL2 Buses at 50 MHz
ATLAS
The signal simulation shows the best placement near the source of the digital signal. The simulation was done before board layout. 11.5. RAM Bus Termination Figure 31 shows an example of the S/UNI-APEX and S/UNI-ATLAS RAM bus termination.
67 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 31.
RAM Bus Termiantion
RAM Bus at 80 MHz Board
NBT SSRAM
SDRAM 22
22
APEX
CMA<19..0>, CBBS<1..0>, CMRWB, MCEB
CBA<11..0>, CBBS<1..0>, CBCSB, CBWEB, CBCASB, CBRASB
SSRAM Bus at 50 MHz
ISD<63..0>, ISP<7..0>, ISADSB, ISRWB, ISOEB 22 ISA<19..0>, ISADSB, ISRWB, ISOEB
PCI9054
ESD<31..0>, ESP<3..0>
Due to space limitations, the termination resistors are placed at the layout convenience and may not be at the best termination position. Typically, address lines and control lines connected to more than two inputs are placed with termination resistor near the signal source. The S/UNI-ATLAS has serial resistors at the data lines ESD<31..0>, ESP<3..0>, ISD<63..0>, and ISP<7..0> that connect point-to-point only, due to observed overshoots on the data edges. The following pages provide examples of the RAM bus signal captured with a digital oscilloscope. Figure 32 shows the waveforms at the S/UNI-APEX and the NBT SSRAM.
68 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
22
ATLAS
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 32.
A
Waveforms at S/UNI-APEX at 80 MHz
B
Graphs A and B show curves that are derived through accumulation of ten consecutive reads from the ZBT SSRAM. The signal integrity is appropriate for this interface. The timing margin, shown in graphB, at about 2.3 ns leaves plenty of room for 0.7 ns hold time specified in the S/UNI-APEX data sheets. Some room on the signal integrity improvement exists on clock waveforms. Other type of buffer and termination resistors may help reduce the overshoot. Figure 33 shows the waveforms at the S/UNI-APEX and the SDRAM.
69 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 33.
Waveforms at SDRAM at 80 MHz
The trace descriptions (next to the right edge of the graph above) apply to the SDRAM pinout shown on the Core Card SDRAM schematics. The clock signal is not shown in the above figure. The oscilloscope captured digital signals show 16 consecutive write cycles to the SDRAM executed by the S/UNI-APEX. The DQ0 trace between 200 ns cursors shows the binary data pattern 1000000000000001 written to the SDRAM. Figure 34 shows the zoomed pattern with clock and timing margins and also shows the waveforms at the S/UNI-APEX and the SDRAM.
70 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 34.
Waveforms at SDRAM at 80 MHz
The digital lines shown above are:
* * *
A0 - address to SDRAM D0 - data to SDRAM WEB - write enable to SDRAM.
The oscilloscope is triggered with the WEB signal. The timing shows about a 2.9 ns margin that is enough for the 1.0 ns hold time for the 100 MHz SDRAM (as specified in the MicronTM data sheets). Figure 35 shows the data flowing from the SDRAM to the S/UNI-APEX.
71 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 35.
Waveforms at S/UNI-APEX at 80 MHz
The digital line, CBDQ<0>, is the data at the S/UNI-APEX coming from the SDRAM. The clock at the S/UNI-APEX pin SYSCLK is about 2.6 ns ahead of the data, leaving enough margin, with a 0.7 ns hold time specified in the S/UNIAPEX data sheets. Figure 36 shows the write to SSRAM (from the S/UNI-ATLAS). The interface runs at 50 MHz.
72 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 36.
Waveforms at SSRAM at 50 MHz
The figure shows digital signals captured during a single write to SSRAM, executed by the S/UNI-ATLAS. The signal integrity is appropriate for this interface. The timing margin at SSRAM is about 4.0 ns, which leaves plenty of room for the 0.5 ns hold time specified in the SSRAM data sheets.
73 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
12.
HARDWARE This section briefly introduces some hardware issues related to the Core Card.
12.1. Card Form The Core Card form factor complies with the PICMG 2.0 Revision 2.1 CompactPCI standard described in document [18]. The Core Card form factor complies with the Hot Swap Specification, PICMG 2.1 Revision 1.0 standard, described in document [19]. 12.2. Front Plate on Core Card The front plates on the Core Card have dimensions specified in the cPCI document [18]. Figure 37 shows an example of the Core Card front plate. Figure 37. Front Plate for Core Card
LEDs
VORTEX 1
DUPLEX
VORTEX 2
Blue LED
Core Card Front Plate
The Core Card is equipped with 18 IEEE 1394 connectors. The top eight connectors support the S/UNI-VORTEX-1 LVDS. The center pair supports the S/UNI-DUPLEX LVDS. The lower eight connectors support the S/UNI-VORTEX-2 LVDS.
74 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The top four rows of the LEDs show the basic status of the Core Card. The blue LED supports software action when the card is inserted and removed. The aluminum front plates are labeled with silkscreen. Labels identify the connectors, LEDs, card type, and manufacturer (PMC-Sierra, Inc.). 12.3. LEDs On the Front Plate The DSLAM Cards are equipped with a set of LEDs. The basic set of four LEDs provides visual information about power lines and the basic condition of the microprocessor interface to all components. The basic LEDs are:
* * *
+5 V, green - indicates a presence of +5 V +3.3 V, green - indicates a presence of +3.3 V uP, red - may not be implemented in the Chipset Driver applications routines. The preferred functionality is that ON indicates trouble at the uP (power-up boot). Status, yellow - is not implemented in Chipset Driver. The preferred functionality is that flashing indicates an operating Core Card, steady indicates a hot stand-by Core Card, and turned off indicates a malfunctioning Core Card. The LED flashes two times per second.
*
The preferred functionality for additional red LEDs is not implemented in the Chipset Driver. The LEDs are intended to indicate a loss of signal (LOS) and a loss of cell delineation (LCD) on the S/UNI-DUPLEX (from the WAN Card) interface. Possible alarms are described as:
* *
LOS1, red - loss of signal at the S/UNI-DUPLEX LVDS RXD1 Port[1] LCD1, red - loss of cell delineation at the S/UNI-DUPLEX LVDS RXD1 Port[1] LOS2, red - loss of signal at the S/UNI-DUPLEX LVDS RXD2 Port[2] LCD2, red - loss of cell delineation at the LVDS RXD2 S/UNI-DUPLEX Port[2]
* *
The preferred functionality for LEDs in the next two rows is showing the status of the LVDS on both the S/UNI-VORTEX-1 and the S/UNI-VORTEX-2. The cPCI specification requires that the blue LED associated with the lower extraction handle be placed next to the handle at the very bottom of the front plate. Figure 38 shows an example of the LED placement on the front plate.
75 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 38.
Example of LEDs Placement
Status uP +3.3V +5V
Basic LEDs
STATUS S/UNI-DUPLEX
LOS1 LCD1 LOS2 LCD2
DUPLEX LEDs
VORTEX LEDs
S/UNI-VORTEX1
S/UNI-VORTEX2
Hot swap blue LED
Core Card
Ejection handle
Two green LEDs, used for supply voltages +5 V and +3.3 V, should not be used as an indicator for accurate voltage level. All other LEDs are controlled with the CPLD and are entirely dependent on the software driver. The blue LED is also software controlled, with the exception of the reset on the host CPU card. The PCI reset turns the LED ON using the PCI9054. The blue LED indicates that the card is not operable when it is inserted or removed from the DSLAM shelf.
76 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
12.4. Printed Circuit Board Stack The board is laid out with 10-layer copper stack. Figure 39 shows an example of the cross-section. Figure 39.
Copper plating 0.5 oz
PCB Cross-section
Layer spacing 4 6 3 6 Layer name
1 2 +3.3 V GND 5 7 - 49.3
Trace width and impedance
9 - 65.3 ;=17 - 50.1 ;= 8 - 50.7
72
1.0 oz
17 6 3 6 4 Traces
6 +3.3 V GND 9 10 8 - 50.7 9 - 65.3 ;=17 - 50.1 ;= 7 - 49.3
0.5 oz
r = 4.5
The ground and power planes are placed at 0.003-inch spacing. This spacing allows for high capacitance (with low parasitic inductance) between the planes, and to create the best filtering of high frequency power rail noise. The +5.0 V and +2.5 V rails are isolated islands, cut out from the +3.3 V copper plane (not shown above). The critical traces for 50 ohm LVDS differential pairs and 65 ohm PCI interface are shown in the most right column. The 50 ohm traces are at 7 to 17 wide, depending on the layer. The 65 ohm PCI interface is laid out only on two external layers. The digital lines are done at about 60 ohms with 5 wide traces on inner layers.
77 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
12.5. Key Coding on the J1 Connector Connector J1 on the Core Card provides the option for keying, which prevents card insertion into an unknown shelf. The Reference Design Core Card is shipped without the key. The Core Card can operate with VI/O at +5 V or at +3.3 V. The cPCI rule-of-the-thumb is to not plug the cPCI card into an unknown shelf! 12.6. Power Supply Specification This section briefly describes some issues related to power supply. 12.6.1. Core Card The Core Card requires a +5 V and 3.3 V supply, fed through cPCI connector J1. Power required for each chip can be estimated using the VORTEX chipset data sheet. The result, though, may be an exaggerated power dissipation, not exactly correlated to measurement in the real system. The total current to the Core Card (board Rev. 3) at +3.3 V rail is about 2.9 A, with traffic at about 40 kcell/s at the S/UNI-ATLAS Ingress input. The safety factor of 40 % brings the current to 4.1 A. The higher safety margin is due to some current changes with supply rail variation. The total current at 5 V rail is about 0.6 A. That current includes the S/UNI-APEX core current at 2.5 V rail. The safety factor of 40 % brings the current to 0.84 A. Total power dissipation on the Core Card, Issue 3, is estimated at P = (5.25 V * 0.84 A) + (3.6 V * 4.1 A) = 19.2 W. The Core Card requires a forced airflow cooling system in enclosed shelves. While the Core Card (board Rev. 3) was tested in an open development shelf, no excessive overheating was observed. The Core Card operates when it is powered with a standard switching power supply found throughout the PC industry.
78 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
12.6.2. S/UNI-DUPLEX and S/UNI-VORTEX The S/UNI-DUPLEX and S/UNI-VORTEX devices need only a single RC filtering element on the CAVD, CAVD0, and CAVD1. The schematic shows zero ohm resistors on other supply rails. Board can be laid out with those rails shorted directly to +3.3 V rail.
79 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
13.
SOFTWARE
13.1. System Processor Requirement The Core Card must be accompanied with a card on the same cPCI shelf. The host processor provides a power-up setup for the DSLAM chipset. The host processor controls operation, alarms and maintenance of the Core Card. 13.2. DSLAM Operating System The DSLAM Reference Design Core Card is run with a software ported on a host processor card with the VxWorks operating system (OS). This is a real-time OS (RTOS). The device drivers for individual chips are also best portable on a platform with the VxWorks. 13.3. Device Drivers PMC-Sierra, Inc. provides, on request, drivers for each DSLAM chipset device that is mounted on the Core Card. PMC-Sierra, Inc. provides, on request, the VORTEX Chipset Driver (board level driver, or metadriver) for the VORTEX chipset that is mounted on the Core Card. 13.4. Example of VORTEX Chipset Setup The following is an example of a possible VORTEX chipset setup sequence on power-up (or reset), executed by the software. This is only an example sequence. For updates to the software drivers, refer to the PMC-Sierra web site regularly. 13.4.1. APEX Setup
* * * * * * * * * * *
Reset chip. Wait for the DLL to run. Do a zero out of all memory apertures. Set up the configuration registers. Set up the cell buffer free list. Set up the shaper. Set up the port. Set up the class. Set up the connection. Enable the interrupts. Enable the queue engine.
80 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
13.4.2. APEX Operations
* * *
Receive or send cells or frames through the SAR interface. Perform a watchdog patrol on FCQ VCs. Set up or tear down ports, classes, and connections dynamically.
13.4.3. DUPLEX and VORTEX Setup
* * * * * * * * *
Reset the chip. Set S/UNI-DUPLEX OCAEN in register 0x0A to 0 (zero). Keep at low through whole initialisation process. Set up the configuration registers. Set up the Logical Channel Base Address and Address Range in VORTEX chips. Set up the Control Channel Base Address in VORTEX chips. Enable the HSS links that are connected to the Line Cards or WAN Cards. Enable polling on S/UNI-ATLAS. Set S/UNI-DUPLEX OCAEN to 1 (one). Enable the interrupts, as needed.
IMPORTANT NOTE: The S/UNI-DUPLEX requires OCAEN bit in register 0x0A to be activated as the very last write, after polling on the S/UNI-ATLAS is enabled. The VORTEX Chipset Driver files vcs_api1.c and dpx.c take care for proper sequencing. Software designers are required to observe sequencing in their drivers.
13.4.4. DUPLEX And VORTEX Operation
*
Receive or send cell or messages through its microprocessor port.
13.4.5. ATLAS Setup
* * * * * * * * *
Reset the chip. Initialise VC tables, and zero out the SSRAM memory. Set up the configuration registers. Set up VC connections including the search tree in the Ingress VC Table. Set up and enable OAM support. Set up PM sessions, if preferred. Set up F4 to F5 processing, if preferred. Enable the interrupts. Enable VCs.
81 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
13.4.6. ATLAS Operations
* * * *
Receive or send cells or frames through its microprocessor interface. You can use the interface for OAM support. Set up or tear down the connections dynamically. The search tree is updated dynamically too. Enable or disable the connections dynamically. Read out the PM record for performance monitoring, if preferred.
13.4.7. Important Notes For Chipset Level Setup
*
* *
*
Make sure the bus interface configuration for the APEX, ATLAS, VORTEX, DUPLEX devices are compatible, and the devices send or transmit cells of the same protocol. (Prepend and H5/UDF bytes be consistent.) Suggest using the same connection ID number for both the APEX and ATLAS VC table index. This simplifies VC management. Suggest using the following algorithm to map the loop port address space: * LoopId[11:0] = VtxId[11:8] | HssLnkId[7:5] | xdslPhyId[4:0]. * the logical channel base address and range in VORTEX devices should be configured appropriately, based on the above loop port mapping algorithm. Suggest using the following search key in ATLAS: * Primary Key = 5 bits PHY ID + 9 bits Field A (embedded address in 9 H5/UDF LSB bits) * Secondary Key = 28 bits of VPI/VCI. No field B.
13.5. Firmware The Core Card has firmware stored in a serial EEPROM that supports the PCI bridge. This device is an 8-pin DIP that is externally programmable and is placed into a socket. 13.6. Programmable Logic Devices The Core Card has a single, in-circuit, programmable CPLD that is permanently assembled (soldered). 13.7. System Control The Core Card provides limited functionality for the system control. The CPU processor can execute a global reset on the WAN Card or Line Card through the
82 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Core Card. This can be done with the S/UNI DUPLEX-DUPLEX or VORTEXDUPLEX LVDS links through the BOC (bit oriented code). The Inband Communication Channel (ICC) allows building custom communication channel between the two DSLAM entities, and in turn, the whole DSLAM system can be in-system reprogrammed and controlled from a single processing center. It is assumed that the microprocessor entities on both sides of the connection are running a reliable communications protocol. This has not been implemented in VORTEX Chipset Driver.
83 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
14.
APPENDIX A: TESTS EXAMPLE UTILIZING CORE CARD DRIVER
14.1. Register and RAM Test with VORTEX Chipset Driver Description: This test uses the VORTEX Chipset Driver functionality and a special test program written in C, creating a primitive text line interface that accesses the Core Card entities. The primary function of this test is to verify the registers on all VORTEX chipset devices and the external RAM on the S/UNI-ATLAS and S/UNI-APEX. The test also verifies (indirectly) the microprocessor interface. The register test derives the expected type and ID bits from the register 0x00 on all VORTEX chipset devices. The RAM test writes, reads, and compares data patterns. Boot the DSLAM shelf with the Core Card from a boot disk and server software. Run the test software routines that use API and metadriver. Type the command names to invoke the test routines from Tcl consloe window (or from a dumb terminal). The Core Card must be in a specific state to run the RAM test, that is, the RAMs are not activated and no traffic is allowed during the RAM test. The test software reports no errors. Register Test. The register test passed on all boards. RAM Test. The initial RAM test provided by the software group passed the S/UNI-ATLAS RAM test. It was later found that the Ingress RAM interface reported a parity error with the traffic test. Investigation on the S/UNI-ATLAS RAM interface showed that the test pattern and read/write sequence was inappropriate. If the RAM is written and read immediately after, it may read correct values even if the RAM chip is removed from the board. This is due to the S/UNIATLAS data drivers indefinitely holding the last written word. The data bus has no pull down/up resistors and the read data may be exactly as the write one. The solution is to write fifteen rows of complimentary hex pattern words (64-bit) to the whole VC Table RAM and then read it. An example of a pattern is shown below.
Stimulus:
Expected Results: Actual Results:
84 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
aaaaaaaaaaaaaaaa (or binary 10101010 ...) 5555555555555555 (or binary 01010101 ...) aaaaaaaaaaaaaaaa .... aaaaaaaaaaaaaaaa 5555555555555555 It is very important to make sure the last word written is complimentary (different) from the first word read. Other patterns can be (hex) C0C0C0... and 030303... . A walking "1" may not find the problem if the read and write follow each other. The improved test and sequence pattern was run again, and a cold solder was found on one of the Ingress RAM leads. 14.2. Cell Data Path with Internal Loopback Test The tests described in this section verify the cell data paths through the Core Card. This is one of the very first data path tests applied to the Core Card on test shelf. The test is very useful to help troubleshoot and verify the basic functionality of the Core Card. The test is executed with test routines written in C. The tests are invoked with Tcl environment through a serial port from the external PC or from a dumb terminal that is connected directly to the host processor card running VxWorks and communicating to the Core Card. The Motorola CPV500 SBC host processor card was used throughout software and hardware development and the test. The cell is generated with the S/UNI-APEX microprocessor interface and received at the same interface. Figure 40 shows the cell path.
85 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Figure 40.
Data Path with Internal Loopback
Diagnostic Loopback on S/UNIVORTEX VORTEX 1
UL2
SSRAM context
SDRAM cell buffer
SSRAM VC table
UL1
Loop Any-PHY TX Master Any-PHY
WAN Any-PHY RX 1 Master
Ingress Out, Slave
Ingress In, Master
Policing
DUPLEX
UL2
Line Cards
2 S/UNI-APEX
Loop Any-PHY RX Slave WAN Any-PHY TX 3 Master
Diagnostic Loopback on S/UNIDUPLEX
S/UNI-ATLAS
Egress In Slave Egress Out Master
VORTEX 2
WAN Card
Microprocessor Interface
PCI9054
cPCI
Host CPU
The cell is always stored in the external Cell Buffer RAM (SDRAM), and then directed to the appropriate port. The test routine allows passing cells on three paths: 1. Microprocessor-to-microprocessor at the S/UNI-APEX only, on path 1. This path is useful for troubleshooting the RAM interface on the S/UNI-APEX. 2. Loopback at the S/UNI-VORTEX 1 or 2 on path 2. The cell tests Any-Phy interface from the S/UNI-APEX to the S/UNI-VORTEX. At the S/UNI_VORTEX, the cell is looped with the Diagnostic Loopback on a chosen high-speed link. The cell travels on the Utopia Level 2 / SCI-PHY bus upstream to the Ingress Input on the S/UNI-ATLAS, and finally on the Utopia Level 1 bus to the S/UNIAPEX. The cell is directed to the microprocessor buffer at the S/UNI-APEX. 3. Loopback at the S/UNI-DUPLEX on path 3. The cell tests the Utopia Level 2 bus upstream from the S/UNI-APEX to the S/UNI-ATLAS. Then the cell travels on the Utopia Level 2 bus to the S/UNI-DUPLEX. At the S/UNI-DUPLEX, the cell is looped with the Diagnostic Loopback on one of two high-speed links. The cell travels downstream to the S/UNI-ATLAS (same interface as the cell on path 2) and finally reaches back to the S/UNI-APEX. The cell is directed to the microprocessor buffer at the S/UNI-APEX.
86 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
UL2
Test Program
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
14.3. External Loopback Test 14.3.1. Sub Test 1: Downstream/Upstream on Sixteen Channels. Description: The test was designed to use the PM1555A ATM over the DS-3 tester. A cell generated with the PM1555A tester travels 32 times through the S/UNI-ATLAS Ingress Input, observed with oscilloscope at the RRDENB line. Each round cell has the VPI/VCI header remapped with the S/UNIATLAS, so it can be sent by the S/UNI-APEX to the appropriate port. The cell goes sixteen times through Loop Tx and sixteen times through the WAN Tx ports. Figure 41 shows the block diagram depicting the test setup. External Loopback with ATM over DS-3 Tester
Q-JET
Figure 41.
LTENB
VORTEX 1
WRENB
S/UNI-APEX
VCI 36 VCI 37 VCI ... VCI 47 48 49 ... 63 33 VCI 33 VCI 34 VCI ... VCI 32 34 ... 32
48, 49, ..., 63 S/UNI-ATLAS
32 VCI, VCT 0
LVDS
RRDENB
ATM over DS-3 tester 0
32, 33, ..., 47
33 VCI, VCT 1 ... VCI, VCT ... 47 VCI, VCT 15 48 VCI, VCT 16 49 VCI, VCT 17 ... VCI, VCT ... 63 VCI, VCT 31
1 DUPLEX DUPLEX 4 3 Software 1 Ports 2
VORTEX 2
3
OAM
WTENB
WAN Card
Downstream Upstream
TABLE 8 shows the parameters from an automatic test that sets sixteen connections in each direction (total of 32).
87 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
DS-3 Ports
TWRENB
VCI 32, 33, 34, 35
LVDS ports loopback
Ports: 0, 1, 2 & 3
VCT 16, VCI 32 VCT 17, VCI 33 VCT ..., VCI ... VCT 31, VCI 32
2
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
TABLE 8.
Input Port Type VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VORTEX 1 VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VORTEX 2 VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT Port #1 0 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 0 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480
Connection Setup
VPI 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 VCI 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VORTEX 2 VORTEX 1 Input Port Type VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_LOOP_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT VCS_WAN_PORT Port #2 0 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 0 VPI 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 VCI 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 32 Table # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
88 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
A test routine sets sixteen ports to/from on the loop side and four ports on the WAN side. The cells from the WAN Card enter the S/UNI-ATLAS with the VCI at 32 through 47. The cells from the loop side (loopback at S/UNI-VORTEX LVDS upstream) enter the S/UNI-ATLAS with the VCI at 48 through 63. All cells have VPI = 100. The parameter Port number #1 specifies the entry port, and Port number #2 specifies the exit port. Ports at the S/UNI-VORTEX1 are distributed across four HSS links with port address 0, 32, 64 up to 480 (this is embedded in Any-PHY ID in the downstream direction and in H5/UDF in the upstream direction). Header remapping is set in the S/UNI-ATLAS. This requires setting the global register 0x200 bit GVPIVCI = 1. Also, the appropriate Header (40) must be entered in the VC Table at row 0111 for each connection. Stimulus: Boot the DSLAM shelf with the Core Card from a boot disk and server software. Run the test software routine vtxcsExtLpbkTest16d x . If cables for external LVDS loopback are not available, then diagnostic loopback on the S/UNI-VORTEX1 and 2 can do the job. Also, Tcl script helps expediting settings. Data throughput is shaped by the S/UNI-APEX, allowing up to 6 Mb/s per connection and allowing total throughput at the WAN Card (Core Card LVDS of about 6 x 16 = 96 Mb/s). The Reference Design Core Card Issue 3 passed the external loopback test with about 6 Mb/s (15 kcell/s) of data at the single DS-3 set at the PM1555A tester. Traffic was set at the PM1555A to below 10 kb/s. FIGURE 1 shows the cell flow that was captured with the oscilloscope.
Expected Results:
Actual Results:
89 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
FIGURE 1.
Cell Flow with External Loopback
The first cell at the RRDENB comes from the WAN Card. The cell passes the S/UNI-ATLAS ingress and is the output from the S/UNI-APEX downstream at LTENB about 19 s later. The cell arrives at the RRDENB about 5.3 s later after loopback at the S/UNI-VORTEX. After 4.9 s, the cell passes the S/UNI-ATLAS and S/UNI-APEX, and shows up at WTENB on the S/UNI-ATLAS Egress Input. Finally, the cell goes in 2.5 s through the S/UNI-ATLAS and is sent on TWRENB to the S/UNI-DUPLEX and next to the WAN card. The WAN Card is loopback with external DS-3 interface, in such a way that ports 2, 3, and 4 (or software ports 1, 2, and 3) loopback to itself. The cells are sent and received at DS-3 port #1 (or software port 0).
90 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
FIGURE 2.
Cell Flow with External Loopback including WAN Card
The WAN Card IENB is at 25 MHz and bus width of 8-bits. Therefore, the IENB signal is four times longer than other signals on the Core Card with the clock at 50 MHz and a bus width of 16-bit. The cell needs about 8.28 s to get from the WAN Card to the RRDENB. The cell goes in 2.4 s to the WRENB - S/UNI-APEX Loop Rx. The cell leaves the S/UNI-APEX 6.36 s later at the LTENB towards S/UNI-VORTEX.
91 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
15.
APPENDIX B: VOLTAGE DISCHARGE ON TRI-STATED BUS The voltage discharge on the tri-stated (high-Z) bus line with pull up/down resistors may cause some problems when the time constant is too long. This refers especially to "cell available" lines, for example, RCA, TPA, TCA, ICA, etc. Analyze the situation when there is no pull-down resistor on the "cell available" line. The slave device is polled and responds with logic high on the "cell available" line and then goes into the high-Z. Capacitance distributed across the bus keeps the logic high for many clock cycles. If on the next address cycle master polls mismatched slave address with no slave responding, then logic high on "cell available" kept by capacitance will fool master and master may initiate non-existing cell transfer. At least one cell cycle is lost, and in the worst condition, unwanted FIFO overflow occurs somewhere. The cell count is increased in the corresponding device. That phenomenon was observed upon development. Inexperienced person may have hard time resolving the problem. With a properly assigned bus poll range and a slave address (channel) range, there should be, in most cases, a device that responds low or high on the "cell available" lines. However, we recommend pull-down resistors on all "cell available" lines. Figure 42 shows the voltage discharge with a different time constant. Figure 42. Voltage Discharge on Hi-Z Bus Line
23 ns
3 .5 3 2 .5 2 [V] 1 .5 1 0 .5 0 0 20
14 ns
67 ns
RC = 10 ns RC = 20 ns RC = 50 ns
2 .V lo g ic "1 "
0 .8 V lo g ic "0 "
40
60
80
100
[n s ]
Vo lta g e d is c h a r g o n H i-Z b u s tra c e
92 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Voltage curves with a time constant at 10 ns, 20 ns, and 50 ns are reaching logic "0" in about 14 ns, 23 ns, and 68 ns respectively. Figure 43 shows an example of a bus at 50 MHz and a simulated discharge after S/UNI-DUPLEX goes into high-Z. Figure 43.
0ns
1 2 A
1 ns 12 ns
Voltage Discharge on Hi-Z Bus Line with Noise
25ns
3 28 ns
50ns
4
75ns
clk1
ICA/TCA
4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 0 20 40 60 80 100
B
RC = 17 ns
[V]
2.V logic "1" 0.8 V logic "0"
[ns]
Voltage discharg on Hi-Z bus trace with 300 mV noise
A 300 mV (150 mV) noise is added making exercise more realistic in a digital environment. For example, assume that the S/UNI-DUPLEX goes into high-Z cycle on the clock edge marked "1". Also, at this point, the bus master starts the valid address poll cycle and checks the response at clock edge "3". After 12 ns, according to the S/UNI-DUPLEX data sheet, the output is tri-stated (marked as "A" above). The logic voltage at about 3.3 V starts dropping exponentially. Signal and noise goes below 0.8 V (TTL logic "low" guaranteed by our I/Os) 28 ns later (marked as "B" above). At this point, the clock edge marks "3" samples for "cell available" and finds the signal as logic "low". If the time constant is longer, as shown in Figure 42, the signal can be sampled as logic "high" fooling bus master.
93 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
The time constant is determined at 17 ns for this exercise. With a small bus consisting of three devices, the total capacitance can be estimated as 3 * 5 pF + 5 pF = 20 pF total. The additional 5 pF is for trace and termination resistors. With this capacitance, the pull-down resistor can be calculated as R = (17 ns) / (20 pF) = 0.85 kohm. With the bus consisting of 10 devices, the total capacitance is above 55 pF, and the pull-down resistor is calculated at R = 0.31 kohm. This resistor value may overload the bus driver and prevent it from delivering logic "high" to the bus line. Designer must verify the cell available signals on a build board. When choosing a resistor value, a compromise should be found. The system designer should make sure the polling address range matches the slave address range to prevent additional bus cycles and prevent the sending of undeliverable cells that take 27 to 29 clock cycles.
94 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
16.
APPENDIX C: EXAMPLE OF SEEP READING ON RESET Figures 12 and 13 (below) show an example of reading SEEP on PCI reset. Both figures show a signal at pins CK (pin2), CS (pin1), and DO/DI (pin3-4), while PCI9054 reads SEEP. Figure 44. Example of SEEP Reading Upon PCI Reset
Figure 45.
Example of SEEP Reading Upon PCI Reset
95 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
17.
APPENDIX D: LOCAL BUS TIMING EXAMPLES 17.1.1. Timing Example for Read from S/UNI-APEX Figure 46 shows an example of a single read from the S/UNI-APEX, captured with a logic analyzer. Due to logic analyzer limitation, the signal abbreviations may not correspond directly to net names on the schematics. Figure 46. Example Read from the S/UNI-APEX at 25 MHz
1
2
3
4
5
6
7
8
The data transfer is started with a PCI5054 setting of L_HOLD high. The S/UNIAPEX asserts the low signal AXRDYB (READYB pin) and AXBTRB (BTERMB pin), which are read into the PCI9054 four clock after line AX_CSB is asserted low. The L_READYB line signals valid data output from the S/UNI-APEX, and that also terminates the data transfer. The PCI9054 de-asserts L_HOLD by toggling it high two clocks later. Read from APEX takes eight clock cycles. L_HOLD stays at the high setting for eight clock cycles. Some jitter on data edges is visible due to a 4 ns logic analyzer resolution.
96 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
17.1.2. Timing Example for Write to S/UNI-APEX Figure 47 shows an example of a single write to the S/UNI-APEX, captured with a logic analyzer. Figure 47. Example Write to APEX Cycle on Local Bus at 25 MHz
1
2
3
4
5
Local address lines L_LA2 and L_LA14 remain steady over three clock cycles, and set the permanent address required for the chip select. Address/Data lines AD2, AD4 and AD7 are all-low with the L_ADSB address strobe at the address cycle (for that particular address) and then toggle to high for the data cycle writing all ones to the S/UNI-APEX. A write to the S/UNI-APEX takes five clock cycles, where L_HOLD stays high for five clock cycles (at 25 MHz clock, 5 x 40 ns = 200 ns).
97 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
17.1.3. Timing Example for Read from S/UNI-DUPLEX Figure 48 shows an example of the access to the S/UNI-DUPLEX. Figure 48. Example Read from the S/UNI-DUPLEX
1
2
3
4
5
6
7
DV_RDB asserted low and DV_WRB asserted high determines the read from the S/UNI-DUPLEX (DV_RDB and DV_WRB - S/UNI-DUPLEX and S/UNI-VORTEX READ or WRITE low). The D_CSB is held low for three clocks, allowing proper access time to the S/UNI-DUPLEX. The L_RDYB goes low, signaling to PCI9054 that data is stable and ready to read. The CPLD internal clocking circuit generates the L_RDYB signal, allowing the slower S/UNI-DUPLEX interface to stabilize data. The chip select line D_CSB goes high at the same clock edge as the L_RDYB. The DV_WRB line going low, at the very beginning and at the very end of the access to the S/UNI-DUPLEX, is an artifact of the internal logic. However, toggling is outside of the active access to the chip. (Toggle due to controlling of the DV_WRB with L_HOLD.) Designer must ensure that timing is not violated on all control lines generated with the CPLD.
98 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
17.1.4. Timing Example for Write to S/UNI-DUPLEX Figure 49 shows an example of a write to the S/UNI-DUPLEX. Figure 49. Example Write to the S/UNI-DUPLEX
Address strobe L_ADSB latches address into CPLD, which in turns generates the chip select to a selected device. The S/UNI-DUPLEX chip select line D_CSB goes low:
* *
Immediately after L_ADSB is deselected Two clocks after bus hold L_HOLD initiates access to the S/UNIVORTEX.
The D_CSB going high latches data into the S/UNI-DUPLEX. At the same clock, CPLD asserts L_RDYB, informing the local bus controller about data being accepted at the S/UNI-DUPLEX and ending the write cycle to the S/UNIDUPLEX. The DX_CSB is held low for two clocks, allowing proper access time to the S/UNI-DUPLEX. CPLD internally generates the delay.
99 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
18.
APPENDIX E: VHDL FOR CPLD The preliminary VHDL source code for the CPLD is shown below. Internal LED D12, D13 and D15 programming variations may occur on particular production runs of the Core Card. Programming of those LEDs have no affect on control functions of the CPLD. Check the PMC-Sierra, Inc. web site for the latest source code.
-- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 1999 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer -- program may be used, modified, reproduced, or distributed in any -- form by any means without the prior written permission of -- PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, -- confidential business information and commercial or financial -- information (collectively, the "Information") of PMC-Sierra, Inc., -- or unlawful disclosure of any or all of the Information may cause -- irreparable harm and result in significant commercial and -- competitive loss to PMC-Sierra, Inc. -- -------------------------------------------------------------------- -------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- -------------------------------------------------------------------- Project : PMC-990815 -- File Name : dslam_core_cpld.vhd -- Path : -- Designer : PMC-Sierra, Inc. --- Revision History -- Issue Date Initials Description -- 1 09/09/99 xx Initial Release --- Function: -- This is the top level of the VHDL code required for the DSLAM CORE
100 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
-- reference design. The code provides control to the micro ports on -- all PMC devices (1 S/UNI-DUPLEX, 2 S/UNI-VORTEXes, 1 S/UNI-ATLAS, -- 1 S/UNI-APEX) present on the DSLAM CORE Card. --------------------------------------------------------------------library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.ALL; ENTITY cccpld IS PORT ( l_clk1 : IN STD_LOGIC; l_la : IN STD_LOGIC_VECTOR(11 DOWNTO 2); l_la_dec : IN STD_LOGIC_VECTOR (2 DOWNTO 0); l_ad : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); l_blastb : IN STD_LOGIC; l_btermb : OUT STD_LOGIC; l_w_rb : IN STD_LOGIC; l_readyb : OUT STD_LOGIC; l_adsb : IN STD_LOGIC; l_waitb : IN STD_LOGIC; l_intb : OUT STD_LOGIC; l_denb : IN STD_LOGIC; l_lserrb : IN STD_LOGIC; l_bhold : IN STD_LOGIC; vx_dx_d : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0); vx_dx_a : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); rstb : IN STD_LOGIC; rstb1 : IN STD_LOGIC; dx_vx_rdb : OUT STD_LOGIC; dx_vx_wrb : OUT STD_LOGIC; dx_csb : OUT STD_LOGIC; vx1_csb : OUT STD_LOGIC; vx2_csb : OUT STD_LOGIC; dx_intb : IN STD_LOGIC; vx1_intb : IN STD_LOGIC; vx2_intb : IN STD_LOGIC; as_busyb : IN STD_LOGIC; as_intb : IN STD_LOGIC; as_wrb : OUT STD_LOGIC; as_rdb : OUT STD_LOGIC; as_csb : OUT STD_LOGIC; ax_csb : OUT STD_LOGIC; ax_wr : OUT STD_LOGIC;
101 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
ax_adsb : OUT STD_LOGIC; ax_burstb : OUT STD_LOGIC; ax_blast : OUT STD_LOGIC; ax_readyb : IN STD_LOGIC; axhi_intb : IN STD_LOGIC; axlo_intb : IN STD_LOGIC; ax_wrdoneb : IN STD_LOGIC; ax_btermb : IN STD_LOGIC; dxrx_8k : IN STD_LOGIC; vx1rx_8k : IN STD_LOGIC; vx2rx_8k : IN STD_LOGIC; ck_8kref : IN STD_LOGIC; ck_8kout : OUT STD_LOGIC; ck_pll_in : OUT STD_LOGIC; ck_pll_out : IN STD_LOGIC; ck_8kout_all : OUT STD_LOGIC; slot6 : IN STD_LOGIC; -- optional; not shown on block diagram type0 : IN STD_LOGIC; -- optional; same type1 : IN STD_LOGIC; -- optional; same ledx1 : OUT STD_LOGIC; ledx2 : OUT STD_LOGIC; ledx4 : OUT STD_LOGIC; leds : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); -- always turned ON with reset ga : IN STD_LOGIC_VECTOR(2 DOWNTO 0) -- optional, not used for this Core Card Issue 3 ); END cccpld; ARCHITECTURE cccpld_arch OF cccpld IS CONSTANT c_REG_ADDR_INTB : STD_LOGIC_VECTOR := "0000000000"; CONSTANT c_REG_ADDR_LED : STD_LOGIC_VECTOR := "0000000001"; CONSTANT c_REG_ADDR_8KHz : STD_LOGIC_VECTOR := "0000000010"; CONSTANT c_REG_INTB : INTEGER := 0; CONSTANT c_REG_LED : INTEGER := 1; CONSTANT c_REG_8KHz : INTEGER := 2; CONSTANT c_BIT_DX_INT_ENB : INTEGER := 13; CONSTANT c_BIT_VX2_INT_ENB : INTEGER:= 12; CONSTANT c_BIT_VX1_INT_ENB : INTEGER :=11; CONSTANT c_BIT_AS_INT_ENB : INTEGER :=10; CONSTANT c_BIT_AXLO_INT_ENB : INTEGER :=9; CONSTANT c_BIT_AXHI_INT_ENB : INTEGER :=8;
102 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
CONSTANT c_BIT_DX_INT : INTEGER :=5; CONSTANT c_BIT_VX2_INT : INTEGER :=4; CONSTANT c_BIT_VX1_INT : INTEGER :=3; CONSTANT c_BIT_AS_INT : INTEGER :=2; CONSTANT c_BIT_AXLO_INT : INTEGER :=1; CONSTANT c_BIT_AXHI_INT : INTEGER :=0; CONSTANT c_BIT_HEADER_8KHz : INTEGER := 0; CONSTANT c_BIT_Pll_0 : INTEGER := 1; CONSTANT c_BIT_Pll_1 : INTEGER := 2; CONSTANT c_ADDR_AX : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; CONSTANT c_ADDR_CPLD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001"; CONSTANT c_ADDR_AS : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010"; CONSTANT c_ADDR_VX1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011"; CONSTANT c_ADDR_VX2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100"; CONSTANT c_ADDR_DX : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101"; CONSTANT c_CLOCK_PERIOD : INTEGER := 40; TYPE STD_LOGIC_2D IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL reg_file : STD_LOGIC_2D; SIGNAL dvas_readyb : STD_LOGIC; SIGNAL dx_vx_as_readyb : STD_LOGIC; SIGNAL dx_select : STD_LOGIC; SIGNAL vx1_select : STD_LOGIC; SIGNAL vx2_select : STD_LOGIC; BEGIN l_ad(7 DOWNTO 0) <= vx_dx_d WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_DX) OR (l_la_dec = c_ADDR_VX1) OR (l_la_dec = c_ADDR_VX2)) ELSE reg_file(c_REG_INTB)(7 DOWNTO 0) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_INTB)) ELSE reg_file(c_REG_LED)(7 DOWNTO 0) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_LED)) ELSE reg_file(c_REG_8KHZ)(7 DOWNTO 0) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_8KHZ)) ELSE "ZZZZZZZZ"; l_ad(15 DOWNTO 8) <= reg_file(c_REG_INTB)(15 DOWNTO 8) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_INTB)) ELSE reg_file(c_REG_LED)(15 DOWNTO 8) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_LED)) ELSE reg_file(c_REG_8KHZ)(15 DOWNTO 8) WHEN l_w_rb = '0' AND l_denb = '0' AND ((l_la_dec = c_ADDR_CPLD) AND (l_la = c_REG_ADDR_8KHZ)) ELSE "ZZZZZZZZ";
103 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
vx_dx_d <= l_ad(7 DOWNTO 0) WHEN l_w_rb = '1' AND l_denb = '0' AND ((l_la_dec = c_ADDR_DX) OR (l_la_dec = c_ADDR_VX1) OR (l_la_dec = c_ADDR_VX2) OR (l_la_dec = c_ADDR_AS)) ELSE "ZZZZZZZZ"; ck_pll_in <= dxrx_8k WHEN reg_file(c_REG_8KHZ)(c_BIT_Pll_0) = '0' AND reg_file(c_REG_8KHz)(c_BIT_Pll_1) = '0' else vx1rx_8k WHEN reg_file(c_REG_8KHz)(c_BIT_Pll_0) = '1' AND reg_file(c_REG_8KHz)(c_BIT_Pll_1) = '0' else vx2rx_8k WHEN reg_file(c_REG_8KHz)(c_BIT_Pll_0) = '0' AND reg_file(c_REG_8KHz)(c_BIT_Pll_1) = '1' else '0'; ck_8kout <= ck_8kref WHEN reg_file(c_REG_8KHz)(c_BIT_HEADER_8KHz) = '0' else ck_pll_out; ck_8kout_all <= ck_8kref WHEN reg_file(c_REG_8KHz)(c_BIT_HEADER_8KHz) = '0' else ck_pll_out; -- This toggles interrupt bits <5..0> c_BIT_xx_xx in register 0x4000 c_REG_INTB reg_file(c_REG_INTB)(c_BIT_DX_INT) <= (NOT dx_intb); reg_file(c_REG_INTB)(c_BIT_VX1_INT) <= (NOT vx1_intb); reg_file(c_REG_INTB)(c_BIT_VX2_INT) <= (NOT vx2_intb); reg_file(c_REG_INTB)(c_BIT_AS_INT) <= (NOT as_intb); reg_file(c_REG_INTB)(c_BIT_AXHI_INT) <= (NOT axhi_intb); reg_file(c_REG_INTB)(c_BIT_AXLO_INT) <= (NOT axlo_intb); l_intb <= (NOT ((NOT dx_intb) AND (reg_file(c_REG_INTB)(c_BIT_DX_INT_ENB)))) AND (NOT ((NOT vx1_intb) AND (reg_file(c_REG_INTB)(c_BIT_VX1_INT_ENB)))) AND (NOT ((NOT vx2_intb) AND (reg_file(c_REG_INTB)(c_BIT_VX2_INT_ENB)))) AND (NOT ((NOT as_intb) AND (reg_file(c_REG_INTB)(c_BIT_AS_INT_ENB)))) AND (NOT ((NOT axhi_intb) AND (reg_file(c_REG_INTB)(c_BIT_AXHI_INT_ENB)))) AND (NOT ((NOT axlo_intb) AND (reg_file(c_REG_INTB)(c_BIT_AXLO_INT_ENB)))); -- LED15 LEDX4, red, also TP_66, inverted l_intb interrupt to PCI9054; always ON with reset ledx4 <= ((NOT rstb) OR NOT ((NOT ((NOT dx_intb) AND (reg_file(c_REG_INTB)(c_BIT_DX_INT_ENB)) )) AND (NOT ((NOT vx1_intb) AND (reg_file(c_REG_INTB)(c_BIT_VX1_INT_ENB) ))) AND (NOT ((NOT vx2_intb) AND (reg_file(c_REG_INTB)(c_BIT_VX2_INT_ENB)))) AND (NOT ((NOT as_intb) AND (reg_file(c_REG_INTB)(c_BIT_AS_INT_ENB)))) AND (NOT ((NOT axhi_intb) AND (reg_file(c_REG_INTB)(c_BIT_AXHI_INT_ENB)))) AND (NOT ((NOT axlo_intb) AND (reg_file(c_REG_INTB)(c_BIT_AXLO_INT_ENB)))))); -- LOS or LCD LEDs, red; always ON with reset leds <= reg_file(c_REG_LED)(13 DOWNTO 0);
104 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
-- LED13 LEDX1, red, all interrupts from chipset together; always ON with reset ledx2 <= ((NOT rstb) OR (NOT (dx_intb AND vx1_intb AND vx2_intb AND as_intb AND axhi_intb AND axlo_intb))); -- LED12, LEDX2, red; access to DUPLEX or VORTEX; always ON with reset ledx1 <= ((NOT rstb) OR dx_vx_as_readyb); -- LED14 LEDX3, red; not connected and not defined dx_select <= '1' WHEN (l_la_dec = c_ADDR_DX) ELSE '0'; vx1_select <= '1' WHEN (l_la_dec = c_ADDR_VX1) ELSE '0'; vx2_select <= '1' WHEN (l_la_dec = c_ADDR_VX2) ELSE '0'; dx_vx_rdb <= NOT ((NOT l_w_rb) AND l_bhold); -- dx_vx_rdb <= '0' WHEN l_w_rb = '0' AND l_bhold = '1' AND ((l_la_dec = c_ADDR_DX) -- OR (l_la_dec = c_ADDR_VX1) OR (l_la_dec = c_ADDR_VX2)) ELSE '1'; dx_vx_wrb <= NOT ((l_w_rb) AND l_bhold); as_rdb <= '0' WHEN l_w_rb = '0' AND l_bhold = '1' AND (l_la_dec = c_ADDR_AS) ELSE '1'; as_wrb <= '0' WHEN l_w_rb = '1' AND l_bhold = '1' AND (l_la_dec = c_ADDR_AS) ELSE '1'; vx_dx_a <= l_la; ax_adsb <= '0' WHEN (l_adsb = '0') AND (l_la_dec = c_ADDR_AX) ELSE '1'; ax_csb <= '0' WHEN (l_adsb = '0') AND (l_la_dec = c_ADDR_AX) ELSE '1'; ax_wr <= l_w_rb; ax_burstb <= '0' WHEN (l_la_dec = c_ADDR_AX) AND (l_bhold = '1') ELSE '1'; -- ax_burstb <= '1'; ax_blast <= l_blastb WHEN (l_la_dec = c_ADDR_AX) AND (l_bhold = '1') ELSE '1'; l_btermb <= ax_btermb WHEN (l_la_dec = c_ADDR_AX) AND (l_bhold = '1') ELSE '1'; l_readyb <= ((ax_readyb AND dx_vx_as_readyb) OR l_denb); PROCESS (rstb, l_clk1) VARIABLE timer : INTEGER RANGE 0 TO 31; BEGIN IF (rstb = '0') THEN dvas_readyb <= '1'; dx_csb <= '1';
105 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
vx1_csb <= '1'; vx2_csb <= '1'; as_csb <= '1'; dx_vx_as_readyb <= '1'; timer := 0; -- Bits 5 downto 0 are set by PMC Devices' INTB output lines. reg_file(c_REG_INTB)(15 DOWNTO 6) <= "0000000000"; reg_file(c_REG_8KHz) <= "0000000000000000"; reg_file(c_REG_LED) <= "0011111111111111"; ELSIF (l_clk1'EVENT AND l_clk1 = '1') THEN IF l_adsb = '0' THEN timer := 0; dx_vx_as_readyb <= '1'; ELSE IF timer < 31 THEN timer := timer + 1; END IF; END IF; CASE l_la_dec IS WHEN c_ADDR_DX => IF l_adsb = '0' THEN dx_csb <= '0'; END IF; IF l_w_rb = '0' THEN IF timer = 2 THEN dx_vx_as_readyb <= '0'; ELSIF timer = 3 THEN dx_csb <= '1'; END IF; ELSE IF timer = 2 THEN dx_csb <= '1'; dx_vx_as_readyb <= '0'; END IF; END IF; WHEN c_ADDR_VX1 => IF l_adsb = '0' THEN vx1_csb <= '0'; END IF; IF l_w_rb = '0' THEN IF timer = 2 THEN
106 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
dx_vx_as_readyb <= '0'; ELSIF timer = 3 THEN vx1_csb <= '1'; END IF; ELSE IF timer = 2 THEN vx1_csb <= '1'; dx_vx_as_readyb <= '0'; END IF; END IF; WHEN c_ADDR_VX2 => IF l_adsb = '0' THEN vx2_csb <= '0'; END IF; IF l_w_rb = '0' THEN IF timer = 2 THEN dx_vx_as_readyb <= '0'; ELSIF timer = 3 THEN vx2_csb <= '1'; END IF; ELSE IF timer = 2 THEN vx2_csb <= '1'; dx_vx_as_readyb <= '0'; END IF; END IF; WHEN c_ADDR_AS => IF l_adsb = '0' THEN as_csb <= '0'; END IF; IF as_busyb = '1' THEN IF l_w_rb = '0' THEN IF timer = 2 THEN dx_vx_as_readyb <= '0'; ELSIF timer = 3 THEN as_csb <= '1'; END IF; ELSE IF timer = 2 THEN as_csb <= '1'; dx_vx_as_readyb <= '0'; END IF;
107 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
END IF; ELSE IF timer > 0 THEN timer := timer - 1; END IF; END IF; WHEN c_ADDR_CPLD => IF l_w_rb = '1' THEN IF timer = 1 THEN dx_vx_as_readyb <= '0'; CASE l_la IS WHEN c_REG_ADDR_INTB => reg_file(c_REG_INTB)(15 DOWNTO 6) <= l_ad(15 DOWNTO 6); WHEN c_REG_ADDR_LED => reg_file(c_REG_LED) <= l_ad; WHEN c_REG_ADDR_8KHz => reg_file(c_REG_8KHz) <= l_ad; WHEN OTHERS => END CASE; END IF; ELSE IF timer = 1 THEN dx_vx_as_readyb <= '0'; END IF; END IF; WHEN OTHERS => END CASE; END IF; END PROCESS; END;
108 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
19.
APPENDIX F: BILL OF MATERIAL Table 9 shows the bill of material (BOM) for the Core Card. TABLE 9. Core Card BOM
Vendor Part No. any Reference Designator C114-C145, C179-C188, C193C214, C244-C251 Qty 72
Item 1.
Description CAPACITOR-1.0 uF, 16 V, Y5V_805 *** due to assembly process, some boards may be assembled with 0.22 uF (read below for more info) CAPACITOR-0.1 uF, 16 V, X7R_603
2.
any
3. 4. 5.
CAPACITOR-4.7 uF, 10 V, TANT TEH any CAPACITOR-68 uF, 6.3 V, TANT TEH any CAPACITOR-0.01 uF, 16 V, X7R_402 any
C2, C3, C80, C86, C146-C153, C174-C178, C189, C190, C192, C215-C227, C229, C233, C236, C237, C240, C241, C260, C261 C235, C238 C239
41
2 1
6. 7.
METALIZED FILM CAPACITOR, 0.015 uF, 16 V, 1206 CAPACITOR-22 uF, 6.3V, TANT TE
PCF1078CT-ND (Digi-Key) any
C5, C6, C8, C10-C16, C18-C29, 157 C31, C32, C34-C53, C57-C79, C81C83, C89, C92, C93, C96-C101, C103-C113, C154, C155, C158, C159, C162-C173, C191, C228, C231, C254, C255, C258, C259, C262, C263, C266-C272, C276, C279-C305, C307-C313 C85, C88 2 C4, C9, C17, C30, C33, C54-C56, C91, C94, C95, C102, C156, C157, C160, C161, C230, C232, C234, C242, C243, C252, C253, C256, C257, C264, C265, C273-C275, C277, C278 D1, D2 D8, D12-D15 D3, D11 D4 D5-D7 D8 D9 J1 32
8. 9. 10. 11. 12. 13. 14. 15.
ZENER DIODE, 150 mW, 10V, SMD LED, SMD, RED SCHOTTKY BARRIER RECTIFIER, 3 A, 20 V, SMD QUAD YELLOW/RED/GREEN/ GREEN LED. QUAD RED LED. SHOTTKY DIODE, LOW CURRENT, 30 mA, 0.30 V, SMD T-1 3/4 LED BLUE VERTICAL PCB MOUNT CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD CONNECTOR ZPACK CPCI 2MM HM 110 POS., TYPE B WITH GND SHIELD HEADER 2, 0.1" SPACING HEADER 2X4 100MIL MALE IEEE 1394-1995 SHIELD RIGHT ANGLE, 2 mm PIN SPACING 3-PIN HEADER. 0.1" SPACING 6-PIN HEADER. 0.1" SPACING
any any SK32DI (digi-Key) SSF-LXH5147LYIGGD (Lumex) SSF-LXH5147IIIID (Lumex) MA732CT LNG995PF9 (PANASONIC) 352068-1 (AMP)
2 5 2 1 3 1 1 1
16.
352152-1 (AMP)
J5
17. 18. 19. 20. 21.
any any 53460-0611 (MOLEX) any any
J45, J65, J72, J73, J74 J36 J46-J63 J64 J66
5 1 18 1 1
109 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
22. 23. 24. 25.
HEADER 1X3, 2 mm HEADER, 1x3, 1.25 mm, MOLEX Ejector handle microswitch, MOLEX OPTIONAL: 38 PIN SIGNAL CONNECTOR, MATCHED iMPEDANCE, 0.025, SMD GENERAL PURPOSE TRANSISTOR, NPN, SOT-23 GENERAL PURPOSE TRANSISTOR, PNP, SOT-23 MOSFET, LOW VOLTAGE 0.007 OHM, 20 V, HEXFET POWER MOSFET 0.047 OHM, 30 V, POWER MOSFET RESISTOR-56, 5 %, 603
any 53047-0310 20817-500 2-767004-2 (AMP)
J6-J35, J37-J44, J67, J68 TP115 OPTIONAL TEST CONNECTORS: J70, J71 Q1 Q4 Q5, Q6, Q7 Q2 Q3
40 1 1 2
26. 27. 28. 29. 30. 31.
MMBT3904LT1 (MOT) MMBT3906LT1 (MOT) ZXM61N0 2F IRL3502S (IR) DI9410 any
1 1 3 1 1
R16, R23, R28, R32-R35, R39-R41, 40 R55-R61, R66, R192, R199, R201, R204, R206, R210, R216, R262, R282-R287, R300, R311, R315, R316, R323, R325, R343, R348 R106, R108, R110, R112, R114, R116, R118, R120, R176, R178, R180, R182, R184, R186, R188, R190, R239, R240 R18, R317, R351 R195, R196 R197, R219, R308-R310, R312, R334 R2, R46, R49, R123, R211, R217, R230, R259, R277-R279, R307, R326, R328, R329 R205 R43, R156, R203, R207, R245, R252, R256, R330 R215 18
32.
RESISTOR-750, 5 %, 603
any
33. 34. 35. 36.
RESISTOR-100 k, 5 %, 603 RESISTOR-200, 5 %, 603 RESISTOR-22, 5 %, 603 RESISTOR-330, 5 %, 603
any any any any
3 2 7 15
37. 38. 39. 40.
RESISTOR-2.2 k, 5 %, 603 RESISTOR-1.0 k, 5 %, 603 RESISTOR-7.5 M, 5 %, 805 RESISTOR-1.00 M, 1 %, 603
any any any any
1 8 1
R22, R36, R37, R45, R47, R62-R65, 72 R67-R84, R87-R89, R128-R154, R157-R159, R193, R194, R212R214, R296, R297, R299, R303R306 R220, R241, R254, R288, R289 R6, R353 R29, R232 R233, R246-R251, R263-R265, R267-R269, R271-R273 R243 R281, R295 R29, R232 R224, R301, R302, R313, R314 R227 R30, R200 (recommended to decrease R200 to 0.005 ohm) R198, R333, R336, R337, R340R342, R355, R27, R44, R51, R124, R125, R221, R231, R274 R54, R127, R234 5 2 2 16 1 2 2 5 1 2 16
41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51.
RESISTOR-820, 5 %, 603 RESISTOR-15 k, 5 %, 603 RESISTOR-220, 5 %, 603 RESISTOR-100, 5 %, 603 RESISTOR-3.0 k, 5 %, 603 RESISTOR-20, 5 %, 603 RESISTOR-220, 5 %, 603 RESISTOR-470, 5 %, 603 RESISTOR-560, 5 %, 603 RESISTOR-0.01, 5 %, 2714 RESISTOR-0, 5 %, 603
any any any any any any any any any any
52.
RESISTOR-0, 5 %, 0805
any
3
110 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
53. 54. 55. 56.
RESISTOR-4.7, 5 %, 0805 RESISTOR-10 M, 5 %, 1206 RESISTOR-10, 5 %, 603 RESISTOR-49.9, 1 %, 603
any any any any
R42, R126, R244 R319-R321 R335
3 3 1
R38, R85, R86, R91, R93, R95, R97, 37 R99, R101, R103, R105, R107, R109, R111, R113, R115, R117, R119, R121, R161, R163, R165, R167, R169, R171, R173, R175, R177, R179, R181, R183, R185, R187, R189, R191, R235, R236 R1, R3-R5, R7-R15, R17, R19, R20, 55 R24-R26, R50, R155, R202, R208, R209, R222, R223, R225, R226, R228, R229, R242, R253, R257, R260, R266, R270, R275, R276, R280, R291-R294, R298, R324, R327, R338, R339, R346, R349, R352, R354, R356, R390, R391 R48, R122, R290 3 R52 R90, R92, R94, R96, R98, R100, R102, R104, R160, R162, R164, R166, R168, R170, R172, R174, R237, R238 RN1, RN6, RN7, RN12-RN17, RN38, RN86, RN89 RN2, RN3, RN25, RN27-RN30, RN32-RN34, RN36, RN37, RN39RN41, RN52, RN54, RN55, RN60RN62, RN64, RN68, RN85, RN91, RN92, RN99, RN100, RN102, RN104-RN10 7, RN111-RN13 5 RN20, RN67, RN69, RN70 RN4, RN5, RN8-RN11, RN18, RN19, RN21-RN24, RN26, RN31, RN35, RN42-RN51, RN53, RN56RN59, RN87, RN108-RN110, RN136-RN139 RN63 RN65, RN66, RN84, RN88, RN90, RN93-RN98, RN101, RN103 RN71-RN83, RN140 U1 U7 U19, U20 U27 U10, U12 U17, U25, U26 U13 U14 U16 U11 1 18
57.
RESISTOR-4.7 k, 5%, 603
any
58. 59. 60.
RESISTOR-4.75 k, 1 %, 603 RESISTOR-4.12 k, 1 %, 603 RESISTOR-430, 5 %, 603
any any any
61. 62.
RES_ARRAY_4_SMD-4.7 k RES_ARRAY_4_SMD-22
any any
12 58
63. 64.
RES_ARRAY_4_SMD-2.2 k RES_ARRAY_4_SMD-56
any any
4 38
65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77.
RES_ARRAY_4_SMD-330 RES_ARRAY_4_SMD-15 k RES_ARRAY_4_SMD-10 S/UNI-ATLAS LAYER SOLUTION S/UNI-APEX ATM TRAFFIC MANAGER S/UNI-VORTEX S/UNI-DUPLEX 3.3 V, 100 MHz, 8MB NBT SRAM (512 k x 18), 119-PBGA VERY HIGH SPEED, QUAD BUFFER WITH THREE STATE OUTPUTS PROGRAMMABLE CLOCK RECOVERY PLL, 20-PIN SMD FAIRCHILD 4 kbit SERIAL EEPROM, 8_PIN DIP, SOCKET, 8-PIN DIP DUAL HOT SWAP CONTROLLER +5 V and 3.3 V SUPERVISING
any any any PM7324 DI (PMC-Sierra, Inc.) PM7326 BI (PMC-Sierra, Inc.) PM7351-BI (PMC-Sierra, Inc.) PM7350-BI (PMC-Sierra, Inc.) GS882Z18B-100 (GSI) SN74ALVC125D (TI) MK2049-01S (ICS Microclock) NM93CS66EN (Fairchild) LTC1645CS8 (LT) LTC1326CMS8 (LT)
1 13 14 1 1 2 1 2 3 1 1 1 1
111 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
CIRCUIT 78. 79. 80. 81. LOW VOLTAGE OP-AMP, RAIL-TORAIL IN/OUT, SOIC8 PACKAGE DUAL 1-TO-5 CLOCK BUFFER REGULATOR, 2.5 V, 800 mA, POSITIVE, LOW DROPOUT MINI-LOGIC, AND GATE, IN SSOP5 PACKAGE, 0.95 MM PIN-SPACING, 3.3 V TO 5 V PCI I/O ACCELERATOR IN-SYSTEM PROGRAMMABLE CPLD, 288 MICROCELLS 3.3V, 100 MHz, 1MB SSRAM (512 k x 36) 3.3 V, 100 MHz, 8 Mbit SDRAM (1Mbit x 4 BANKS x 16 WIDE) EPSON 12.288 MHz CRYSTAL TLV2461CD (TI) QS53805 (Quality Smi.) LT1118CST-2.5 (LT) TC7S08FCT (Toshiba) U18 U2, U3 U21 U22, U23 1 2 1 2
82. 83. 84. 85. 86. 87. 88. 89. 90. 91.
PCI9054-AA50PI (PLX) XC95288XL-10TQ144 C (Xilinx) GS88036T-100 (GSI) MT48LC4M16A2-75 (Micron) MA-505-12.288M-C2 (Epson)
U15 U31 U4-U6 U8, U9 Y1 Y2 Y3, Y5 Y4 C1, C7, C84, C87, C90 R21, R31, R53, R218, R255, R258, R261, R318, R322, R331, R332, R344, R345, R347, R350 L1, Q4
1 1 3 2 1 1 2 1
OSCILLATOR, 50 MHz, 3.3 V, 50PPM CB3LV-3C-50.0000- T OSCILLATOR, 25 MHz, 3.3 V, 50PPM CB3LV-3C-25.0000- T OSCILLATOR, 80 MHz, 3.3 V, 50PPM CB3LV-3C-80.0000- T N/u N/u
92. 93. 94.
N/u
Not a part - pads for optional wire DP1, DP2, ZQ1, ZQ2 strapping Not a part - optional test pads, A0, ADSC1, ADSC2, AS_ICLK, BA0, mounting holes, or wiring pads BA1, CAS, CE1, CKL3, CLK, CLK4, CMA0, CMD0, CS, DQ, DQ0, D_CLK, ESA0, ESA16, ESD0, ESP0, GND1-GND4, GW1, GW2, ISA0, ISA16, ISD0, ISP0, OE1, OE2, RAS, RW, TP1-TP3, TP7-TP17, TP21-TP32, TP35-TP37, TP42TP49, TP66-TP69, TP72-TP76, TP78, TP79, TP81-TP117 , TP_2.5V, TP_3.3V, TP_RSTB, TP_VCC, WE, DP1, DP2, FT1, FT2, JP1-JP4, JP8, JP9, JP11-JP13, JP16-JP18, VDD1, VDD2, ZQ1, ZQ2 M1, P1
95.
***/ Due to assembly process, some boards may have serial LVDS capacitors assembled with 0.22 uF. It is recommended to observe baseline wander in real systems, and possibly increase capacitor value to 1.0 uF. That may be especially important if LVDS is run at slower speed, i.e. 100 Mbps (our Core Card runs at 200 Mbps).
112 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
20.
APPENDIX G: SCHEMATIC DIAGRAMS The Core Card schematic pages are organized by blocks, as shown in the "Core Card Root Drawing", page 1. Each block may have one or two pages. If two pages are in a single block, then each page has the additional number 1 or 2 shown on each page title, for example, S/UNI-APEX 1 and S/UNI-APEX 2. The interconnections between blocks are marked with the suffix "\I", for example, RSTB\I, L_AD<31..0>\I, etc. Interconnections on the same page or between two pages in the same block do not have the suffix, for example, L_BTERMB, L_DENB, etc: All interconnections with the suffix "\I" on individual pages are shown in "Core Card Root Drawing" on page 1. However, page 1 netlists do not show the suffix "\I" (the way Concept CAD tool works). Single page or single block connections are not shown on page 1. Page 1: Root drawing with interconnections between blocks. Page 2 - FRONT: IEEE 1394 LVDS connectors, front panel LEDs, blue LED and ejector switch header Page 3 - S/UNI-VORTEX2 BLOCK: S/UNI-VORTEX 2, page 1, digital subblocks and power. Page 4 - S/UNI-VORTEX2 BLOCK: S/UNI-VORTEX 2, page 2, LVDS ports. Page 5 - S/UNI-DUPLEX: S/UNI-DUPLEX, LVDS ports, digital sub-blocks and power. Page 6 - S/UNI-VORTEX1 BLOCK: S/UNI-VORTEX 1, page 1, digital subblocks and power. Page 7 - S/UNI-VORTEX1 BLOCK: S/UNI-VORTEX 1, page 2, LVDS ports. Page 8 - S/UNI-APEX BLOCK: S/UNI-APEX 1, page 1, digital sub-blocks and power. Page 9 - S/UNI-APEX BLOCK: S/UNI-APEX 1, page 2, RAM interfaces. The RAM size for the S/UNI-APEX is shown for exercise purposes only. The circuit supports the BGA package. The smaller size NBT (ZBT) SSRAMs may be available in TQFP packages only. The RAM size for the S/UNI-APEX should be calculated as explained in [7] and [12], depending on the system requirements. Page 10 - S/UNI-ATLAS BLOCK: S/UNI-ATLAS 1, page 1, digital sub-blocks and power.
113 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Page 11 - S/UNI-ATLAS BLOCK: S/UNI-ATLAS 2, page 2, RAM interfaces. Page 12 - J1, PCI, PCI9054 & CPLD: PCI_CPLD 1, page 1, cPCI interface over J1 and PCI9054 bridge. Page 13 - J1, PCI, PCI9054 & CPLD: PCI_CPLD 2, page 2, CPLD, 8 kHz PLL, test connectors. Page 14 - J5 CONNECTOR: J5 LVDS connector, Hot-Swap circuit, RESET. Resistor R200 should be decreased to 0.005 ohm to have lower voltage drop.
2.5 V U21 5.0 V C239 MOSFET DI9410 "+5 V" 0.01 ohm 0.3 A Backplane "+3.3 V" 2.7 A Backplane
0 mV
9.0 mV
7.0 mV
3.0 mV
8.0 mV
10.0 mV 27 mV MOSFET IRL3502S C242 C4
TP 3.3 V
R200 0.01 ohm
0 mV 2.2 mV
2.6 mV
5.0 mV
2.5 mV
13.9 mV 34.2 mV 48.1 mV
10.0 mV
70.4 mV
The hot swap controlling elements introduce 48.1 mV voltage drop for 3.3 V rail. . That is too close to current sensing threshold on LTC1645. Page 15 - Signal cross-reference: Optional page helping finding netlists names. Page 16 - Component cross-reference: Optional page to help find components names. Page 17 - Component cross-reference: Optional page to help find components names. Page 18 - Component cross-reference: Optional page to help find components names.
114 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
21.
APPENDIX H: LAYOUT The layout section contains:
* * * * * * * *
drawing summary report x-y coordinates pages mechanical drawing page top component placement page top silk screen page copper layers, ten pages bottom silk screen page bottom component placement page
21.1. Drawing Summary Report
|------------------------------------------------------------------------------| | | | | Drawing Extents XL -4900.000 YL -6600.000 W:\pcb8\pcb\dslam_core.brd Wed May 03 11:08:26 2000 XU 17100.000 YU 10400.000 DRAWING SUMMARY REPORT Page 1 | | | |
|------------------------------------------------------------------------------|
|------------------------------------------------------------------------------| Dimensions in mils with 3 decimal places -----------------------------------Package Symbols: 1115 Total 12 Total 1 0 Errors 62 Definitions Assigned 1558 Unassigned 0 Total 1558 424 Mirrored 6083 8 Pins Pins -----------------------------------Mechanical Symbols: Format Symbols: DRC: Padstacks: Functions: --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
115 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
Layout Statistics: ----------------Components: Nets: Pins: RatTs Connection Statistics: ---------------------Connections Already Connected Missing Connections Connection Completion Manh Distance (inches) Etch Length (inches) Number of vias Vias per Connection Placed 1115 Unplaced 0 Total 1115 Unplaced 0 Total 6079 W/Rats 1546 W/Rats 5508 No/Rats 1 Total 1547 Unused 423 434 No/Rats ------147 147 0 100.00% 23.88 0 1.07 0.00 Total ----4109 4109 0 0 100.00% 3305.10 4263 1.03 4909 #shapes (voids) 8(0) 1(88) 3(3644) 1(3941) 0(0) 0(0) 4(3907) 3(3644) 1(80) 0(0) #rectangles 0 0 0 0 0 0 0 0 0 0 #non-connect lines/arcs 1 1 1 1 1 1 1 1 1 1 #text 3 3 3 3 3 3 3 3 3 3 Page 2 | |
No/Rats 148 0 W/Rats -----3962 3962 0
Equivalent ICs (1 pin = 1/14 EIC)
Dangling Connections (See logfile) 100.00% 3290.61 3281.20 4263
Smd pins with attached clines Etch: TOP SIG1 GND_PLANE 3V3_PLANE SIG2 SIG3 3V3_A_PLANE GND1_PLANE SIG4 BOTTOM | | #connect lines/arcs 3869 402 289 32 473 395 32 288 308 1640
------------------------------------
|------------------------------------------------------------------------------| DRAWING SUMMARY REPORT W:\pcb8\pcb\dslam_core.brd etch totals 7728 21(15304) End Summary 0 Report |------------------------------------------------------------------------------| Wed May 03 11:08:26 2000 10 30 |------------------------------------------------------------------------------| |--------------------------------------------------|
21.2. X-Y Coordinates for Issue 3 Board Following pages show X-Y coordinates for components placed on Issue 3 board.
116 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
X-Y Coordinates for components on Core Card Issue 3
Y 0, 0 X
UUNITS = MILS (e.g. 4160 = 4.160 inch) Component A0 ADSC1 ADSC2 AS_ICLK AX_WAN BA0 BA1 C1 C10 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109 C11 C110 C111 C112 C113 C114 C115 C116 C117 C118 C119 C12 C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C13 C130 C131 X -880 4160 6920 3365 280 -800 -800 3415 4945 3300 2950 2410 3800 3225 3125 3975 3825 6995 6320 4375 5595 6570 6845 5995 2275 2350 2437.5 2512.5 1900 1975 3500 2062.5 2137.5 1525 1600 1687.5 1762.5 1150 1225 1312.5 1387.5 4325 675 750 Y Footprint 3960 TST_PT_PAD50CIR32D 1200 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 2705 TST_PT_PAD50CIR32D 2825 TST_PT_PAD50CIR32D 3960 TST_PT_PAD50CIR32D 3880 TST_PT_PAD50CIR32D 630 603 380 402 4300 402 4450 402 680 SMDTANCAP_B 3575 402 4475 402 4100 402 4475 402 3950 402 3920 402 4480 402 975 402 4020 402 4495 402 4295 402 3920 402 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 1365 402 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 5612.5 SMDCAP805 2425 402 5612.5 SMDCAP805 5612.5 SMDCAP805
C132 C133 C134 C135 C136 C137 C138 C139 C14 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C15 C150 C151 C152 C153 C154 C155 C156 C157 C158 C159 C16 C160 C161 C162 C163 C164 C165 C166 C167 C168 C169 C17 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C18 C180 C181 C182 C183 C184 C185 C186 C187 C188 C189 C19 C190
837.5 912.5 300 375 462.5 537.5 -75 0 3150 87.5 162.5 -450 -375 -287.5 -212.5 4052.5 3902.5 3752.5 3502.5 4650 3350 3102.5 2952.5 2802.5 6720 6670 3227.5 7045 5982.5 6345 3755 6282.5 5580 5995 6020 6870 6195 5770 6690 6095 6685 2510 5820 6495 4345 4775 -12.5 -627.5 112.5 132.5 -72.5 6525 5645 6600 6687.5 6762.5 6150 6225 6312.5 6387.5 5775 5850 402.5 4100 -172.5
5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 1725 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 4790 4790 4790 4790 2225 4795 4790 4790 4790 3645 3395 4727.5 3940 4095 3420 1365 4532.5 3990 3620 3395 3220 4115 3245 3770 4295 4070 4720 4270 4120 3650 3410 785 1165 1795 810 1815 5612.5 1775 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 1200 1725 785
SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 402 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 603 603 603 603 402 603 603 603 603 402 402 SMDTANCAP_B SMDTANCAP_B 402 402 402 SMDTANCAP_B SMDTANCAP_B 402 402 402 402 402 402 402 402 SMDTANCAP_B 402 402 402 402 603 603 603 603 603 SMDCAP805 402 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 603 402 603
117 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
C191 C192 C193 C194 C195 C196 C197 C198 C199 C2 C20 C200 C201 C202 C203 C204 C205 C206 C207 C208 C209 C21 C210 C211 C212 C213 C214 C215 C216 C217 C218 C219 C22 C220 C221 C222 C223 C224 C225 C226 C227 C228 C229 C23 C230 C231 C232 C233 C234 C235 C236 C237 C238 C239 C24 C240 C241 C242 C243 C244 C245 C246 C247 C248 C249
1825 -925 5937.5 6012.5 5400 5475 5562.5 5637.5 4925 2940 5200 5000 5087.5 5162.5 4550 4625 4712.5 4787.5 4175 4250 4337.5 3750 4412.5 3800 3875 3962.5 4037.5 7070 7070 6810 -825 1125 5725 1125 -212.5 6660 6370 6150 6010 402.5 -627.5 1825 5860 3495 2750 2125 1970 1200 1965 1100 3605 1510 1215 382.5 4475 1125 3705 2090 7205 3225 3300 3387.5 3462.5 2850 2925
4300 410 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 2355 1130 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5 2085 5612.5 5612.5 5612.5 5612.5 5612.5 4205 4550 4645 410 300 1075 200 1815 4645 4585 4645 4645 1360 1575 3525 4645 2085 800 4300 3140 0 3920 25 260 2830 455 2645 1075 425 255 5 3260 5612.5 5612.5 5612.5 5612.5 5612.5 5612.5
402 603 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 603 402 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 402 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 603 603 603 603 603 402 603 603 603 603 603 603 603 603 402 603 402 SMDTANCAP_B 402 SMDTANCAP_B 603 SMDTANCAP_B SMDTANCAP_B 603 603 SMDTANCAP_B NEC_D 402 603 603 SMDTANCAP_B SMDTANCAP_B SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805 SMDCAP805
C25 C250 C251 C252 C253 C254 C255 C256 C257 C258 C259 C26 C260 C261 C262 C263 C264 C265 C266 C267 C268 C269 C27 C270 C271 C272 C273 C274 C275 C276 C277 C278 C279 C28 C280 C281 C282 C283 C284 C285 C286 C287 C288 C289 C29 C290 C291 C292 C293 C294 C295 C296 C297 C298 C299 C3 C30 C300 C301 C302 C303 C304 C305 C307 C308
4800 3012.5 3087.5 7275 5510 3595 3855 6532.5 5221.5 5165 5170 5400 4725 4931.5 5165 5165 5220 5221.5 4990 4695 4556.5 4757 5825 4919 5087.5 4911.5 5221.5 800 1350 5036.5 1100 1325 3595 5645 3855 -175 -270 -435 -450 -590 -180 -900 -630 -165 5725 -920 -165 -450 -435 1750 2555 2200 2205 2300 1830 4230 6045 1485 1430 2300 1820 1295 595 2295 2555
1130 5612.5 5612.5 1825 3700 2860 2860 4532.5 4530 4550 4190 2225 4650 4650 4430 4320 4150 4405 4450 4320 4100 4027 2425 3960 4164 4280 4280 2900 2900 4040 3125 3125 2460 2125 2460 5045 3235 4045 3235 4090 3785 4595 3230 4045 2325 3780 4590 3785 4590 3675 4150 3600 4370 3400 2040 2175 675 2045 1090 1437.5 1060 1770 5190 4190 3375
402 SMDCAP805 SMDCAP805 SMDTANCAP_B SMDTANCAP_B 402 402 SMDTANCAP_B SMDTANCAP_B 402 402 402 603 603 402 402 SMDTANCAP_B SMDTANCAP_B 402 402 402 402 402 402 402 402 SMDTANCAP_B SMDTANCAP_B SMDTANCAP_B 402 SMDTANCAP_B SMDTANCAP_B 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 603 SMDTANCAP_B 402 402 402 402 402 402 402 402
118 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
C309 C31 C310 C311 C312 C313 C32 C33 C34 C35 C36 C37 C38 C39 C4 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C5 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C6 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C7 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C8 C80 C81 C82 C83 C84 C85
1750 5550 1745 2545 2550 1750 375 -200 775 975 1025 120 1375 1220 1915 375 5000 525 575 925 225 1460 1220 4550 625 -860 1350 1125 225 1455 4130 -350 2725 4550 120 4425 2825 4550 5645 2425 5825 6570 6225 6825 6830 6570 6415 260 7180 7175 6830 6570 6225 6980 4150 3265 2750 3665 2150 3450 2900 3850 3850 3565 2950
4100 1130 3320 4455 3685 4450 3925 2600 3480 3220 4325 3475 4500 4230 5 3675 2225 4325 4325 4325 4500 4100 4125 1575 3220 450 3325 3480 3350 3695 2765 4900 2675 1975 4075 2325 190 1225 1575 4300 975 2610 1375 2610 1015 1890 1735 5190 2250 1375 1890 1015 2250 1735 4100 4690 4175 4690 3550 950 3400 3825 4275 730 885
402 402 402 402 402 402 402 SMDTANCAP_B 402 402 402 402 402 402 SMDTANCAP_B 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 SMDTANCAP_B SMDTANCAP_B SMDTANCAP_B 402 402 402 402 402 402 402 402 402 402 402 402 402 402 SMDCAP805 402 402 402 402 402 402 402 402 402 402 402 603 402 402 402 SMDCAP805 SMDCAP1206
C86 3075 C87 3505 C88 2850 C89 2425 C9 600 C90 2935 C91 4195 C92 4000 C93 3600 C94 3627.5 C95 2700 C96 3475 C97 3150 C98 3125 C99 3100 CAS -640 CE1 2440 CKL3 4165 CLK 2200 CLK4 7000 CMA0 2360 CMD0 2120 CS -720 D1 2205 D11 -25 D12 2225 D13 2095 D14 1965 D15 1835 D2 1490 D3 2530 D4 7575 D5 7175 D6 6975 D7 7375 D8 2355 D9 -625 DP1 2270 DP2 2020 DQ -560 DQ0 25 DX_VX_RDB 5425 DX_VX_WRB 5600 ESA0 4070 ESA16 4070 ESD0 4070 ESP0 4070 FT1 2145 FT2 2735 GND1 -560 GND2 2520 GND3 3075 GND4 6680 GW1 4160 GW2 6760 ISA0 6520 ISA16 6440 ISD0 6600 J1 0 J10 7370.496 J11 7370.496 J12 7370.496 J13 7370.496 J14 7420.5 J15 7499.5
1000 603 875 603 885 SMDCAP1206 3525 402 500 SMDTANCAP_B 1160 SMDCAP805 4125 SMDTANCAP_B 3400 402 4320 402 4727.5 SMDTANCAP_B 4150 SMDTANCAP_B 3600 402 3575 402 3800 402 4275 402 3880 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 1660 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 3880 TST_PT_PAD50CIR32D 750 SOD323 3050 SMC_2 2350 LED_11 2350 LED_11 2350 LED_11 2350 LED_11 -25 SOD323 310 SMC_2 6017.5 SSF-LXH5147 6017.5 SSF-LXH5147 6017.5 SSF-LXH5147 6017.5 SSF-LXH5147 2350 LED_11 5840 LED_5MM 4485 JUMPER_3PIN_INLINE 3275 JUMPER_3PIN_INLINE 3960 TST_PT_PAD50CIR32D 4450 TST_PT_PAD50CIR32D 3675 TST_PT_PAD50CIR32D 3430 TST_PT_PAD50CIR32D 1120 TST_PT_PAD50CIR32D 1200 TST_PT_PAD50CIR32D 1280 TST_PT_PAD50CIR32D 1370 TST_PT_PAD50CIR32D 4485 JUMPER_3PIN_INLINE 3575 JUMPER_3PIN_INLINE 3880 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 1925 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 1370 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 88.583 ZPACK5X22FH_ASCPCI 4284.5 HEADER3_2MM 4205.5 HEADER3_2MM 4482 HEADER3_2MM 4403 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM
119 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J41 J42 J43 J44 J45 J46 J47 J48 J49 J5 J50 J51 J52 J53 J54 J55 J56 J57 J58 J59 J6 J60 J61 J62 J63 J64 J65 J66 J67 J68 J7 J70 J71 J72 J73 J74 J8 J9 JP1 JP11
7223 7302 7025.5 7104.5 6828 6907 6630.5 6709.5 6433 6512 6235.5 6314.5 6038 6117 5840.5 5919.5 5643 5722 5445.5 5524.5 995 5248 5327 4487 4566 4289.5 4368.5 4882 4961 4250 6265 5515 4665 3915 7100.394 2015 1265 415 -335 6640 5890 5040 4290 2390 1640 7370.496 790 40 2965 3340 -825 2775 5300 4684.5 4763.5 7370.496 925 2650 2775 2080 2210 7370.496 7370.496 -785 6715
4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 895 HEADER_4X2 4920.496 HEADER3_2MM 4920.496 HEADER3_2MM 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 4450 HEADER_2 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 88.583 ZPACK5X22FH_BSCPCI 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 3889.5 HEADER3_2MM 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 5944 MOLEX53460_0611 587.5 JUMPER3 1350 HEADER_2 475 SIP6 4950.496 HEADER3_2MM 4950.496 HEADER3_2MM 3810.5 HEADER3_2MM 1850 MICTOR_38_PIN 1950 MICTOR_38_PIN 1125 HEADER_2 3030 HEADER_2 2525 HEADER_2 4087 HEADER3_2MM 4008 HEADER3_2MM 3125 JUMPER_3PIN_INLINE 2700 JUMPER_3PIN_INLINE
JP12 JP13 JP16 JP17 JP18 JP2 JP3 JP4 JP8 JP9 L1 LA2 LTADR0 LTENB M1 OE1 OE2 P1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 R1 R10 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R11 R110 R111 R112 R113 R114 R115 R116 R117 R118 R119 R12 R120 R121 R122 R123 R124 R125 R126 R127 R128 R129 R13 R130 R131 R132 R133 R134
7115 5590 580 4395 5 1780 2220 1785 6450 1325 3485 4195 5900 6060 7868.11 4160 6840 -917.322 3100 1715 2235 3100 -50 -195 135 3100 5580 3140 3140 2990 2990 2765 2840 4090 4015 3865 3865 545 3715 3715 3540 3465 3315 3315 3065 3065 2915 2915 397.5 2840 2765 6257.5 6645 5595 6995 6530 6270 5937.5 5400 342.5 5562.5 4925 5087.5 4550 4712.5
1800 JUMPER_3PIN_INLINE 725 JUMPER_3PIN_INLINE 1190 JUMPER_3PIN_INLINE 4630 JUMPER_3PIN_INLINE 2625 JUMPER_3PIN_INLINE 3920 JUMPER_3PIN_INLINE 2085 JUMPER_3PIN_INLINE 3140 JUMPER_3PIN_INLINE 915 JUMPER_3PIN_INLINE 1145 JUMPER_3PIN_INLINE 600 SMDCAP1206 1845 TST_PT_PAD50CIR32D 2950 TST_PT_PAD50CIR32D 2950 TST_PT_PAD50CIR32D 6020.860 MOUNT_HOLE_150 1280 TST_PT_PAD50CIR32D 1800 TST_PT_PAD50CIR32D 3006.889 CPCI_ESD_STRIP 125 SOT23 292.5 D2PAK 520 SO8NB-3 325 SOT23 1315 SOT23 1350 SOT23 1300 SOT23 225 603 3495 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 1115 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 2025 603 4690 603 4690 603 4057.5 603 3632.5 603 3970 603 3970 603 4500 603 4520 SMDRES805 5637.5 603 5637.5 603 2025 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603
120 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
R135 R136 R137 R138 R139 R14 R140 R141 R142 R143 R144 R145 R146 R147 R148 R149 R15 R150 R151 R152 R153 R154 R155 R156 R157 R158 R159 R16 R160 R161 R162 R163 R164 R165 R166 R167 R168 R169 R17 R170 R171 R172 R173 R174 R175 R176 R177 R178 R179 R18 R180 R181 R182 R183 R184 R185 R186 R187 R188 R189 R19 R190 R191 R192 R193
4175 4337.5 3800 3962.5 6600 -575 6762.5 6225 6387.5 5850 6012.5 5475 5637.5 5000 5162.5 4625 -675 4787.5 4250 4412.5 3875 4037.5 4825 3605 3225 3387.5 2850 7050 7069 7019 7069 7019 6770 6845 6620 6695 6405 6450 -612.5 6195 6195 6045 6045 5895 5895 7069 7019 7069 7019 -925 6845 6770 6695 6620 6450 6370 6115 6115 5970 5970 1100 5820 5820 1925 3012.5
5637.5 5637.5 5637.5 5637.5 5637.5 2625 5637.5 5637.5 5637.5 5637.5 5637.5 5637.5 5637.5 5637.5 5637.5 5637.5 2625 5637.5 5637.5 5637.5 5637.5 5637.5 350 135 5637.5 5637.5 5637.5 3675 4063.5 4063.5 4401 4401 4575 4515 4590 4520 4660 4525 1050 4565 4495 4555 4495 4555 4495 4138.5 4138.5 4476 4476 900 4575 4515 4590 4520 4585 4525 4565 4495 4555 4495 250 4555 4495 2875 5637.5
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
R194 R195 R196 R197 R198 R199 R2 R20 R200 R201 R202 R203 R204 R205 R206 R207 R208 R209 R21 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R22 R220 R221 R222 R223 R224 R225 R226 R227 R228 R229 R23 R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 R24 R240 R241 R242 R243 R244 R245 R246 R247 R248 R249 R25 R250 R251
3300 6475 6400 452.5 1237.5 1237.5 5350 1100 1385 2250 680 2375 4125 6550 2575 2575 6020 4925 2725 2575 5275 3462.5 2925 3087.5 2905 3300 1100 2760 745 6525 830 2752.5 2925 2925 2355 500 3215 4710 5875 325 4740 1075 5180 3940 -750 5200 4795 4860 4656.5 4860 4581.5 915 4795 4910 4340 -650 5180 -550 7750 1400 1462.5 1525 765 1587.5 1650
5637.5 425 425 2025 1392.5 1267.5 2150 175 430 3025 1105 2700 3825 425 1050 1125 3720 475 4395 1350 2150 5637.5 5637.5 5637.5 835 1275 4725 300 1105 5637.5 3600 72.5 225 150 2525 3550 405 3750 260 4675 3660 4675 4510 615 5625 4265 4650 4650 4650 4650 4650 410 4650 2635 4010 5625 4380 5625 5750 925 925 925 410 925 925
603 603 603 603 603 603 603 603 POWERRES_2714 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 SMDRES805 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 SMDRES805 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
121 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
R252 R253 R254 R255 R256 R257 R258 R259 R26 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R27 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R28 R280 R281 R282 R283 R284 R285 R286 R287 R288 R289 R29 R290 R291 R292 R293 R294 R295 R296 R297 R298 R299 R3 R30 R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 R31
3780 3340 4855 1225 2925 3100 2925 500 4175 1375 2925 1925 1712.5 1900 1837.5 1300 1775 1962.5 2025 4150 1150 2087.5 2150 2212.5 5180 5056.5 4375 4375 4375 4925 2410 4375 3605 275 275 750 750 275 275 4850 3735 3175 4785 5000 5006.5 4875 4375 4375 912.5 375 3150 537.5 5325 2175 4375 2225 2095 0 162.5 -375 -212.5 5200 550 4925 1237.5
255 495 2635 4675 -50 25 365 3500 2100 4675 75 2800 925 925 925 4675 925 925 925 4150 4675 925 925 925 4140 4650 4275 4212.5 4075 3825 1470 4335 5 4950 5100 5000 4850 4875 5025 1425 3675 1275 4320 3825 4650 3825 4275 4400 5637.5 5637.5 3900 5637.5 2600 205 4475 2185 2185 5637.5 5637.5 5637.5 5637.5 2150 1025 1275 1330
603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 POWERRES_2714 603 603 603 603 603 603 603 603 603 603 603
R310 R311 R312 R313 R314 R315 R316 R317 R318 R319 R32 R320 R321 R322 R323 R324 R325 R326 R327 R328 R329 R33 R330 R331 R332 R333 R334 R335 R336 R337 R338 R339 R34 R340 R341 R342 R343 R344 R345 R346 R347 R348 R349 R35 R350 R351 R352 R353 R354 R355 R356 R36 R37 R38 R39 R390 R391 R4 R40 R41 R42 R43 R44 R45 R46
5000 4850 6085 1965 1835 725 5600 4725 2410 -925 1925 -900 -800 180 5225 4375 650 5150 1110 5250 5390 2375 5100 5300 5440 1900 6085 985 2425 2625 1600 1840 2375 1895 2455 2625 755 1710 3565 -105 1775 2915 -295 4740 -230 865 -45 100 245 35 4895 6687.5 6150 5190 4770 2575 2575 5125 5190 5190 3615 -475 840 6312.5 485
1275 1275 2225 2185 2185 3600 2825 475 3740 2300 2675 5125 5125 5095 2600 4150 4105 590 4325 590 590 2775 590 590 590 4565 2290 410 4565 4070 4450 3250 2625 3120 3235 3900 5065 4530 800 1145 3075 1045 1190 3560 1190 1125 1145 1145 1330 1145 600 5637.5 5637.5 3435 3750 1200 1275 2150 3660 3510 4690 2625 410 5637.5 4730
603 603 603 603 603 603 603 603 603 SMDRES1206 603 SMDRES1206 SMDRES1206 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603 603
122 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
R47 R48 R49 R5 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R6 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R7 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R8 R80 R81 R82 R83 R84 R85 R86 R87 R88 R89 R9 R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 RADDR0 RAS RN1 RN10 RN100 RN101 RN102
5775 3390 3737.5 5250 4125 2750 3100 2925 3202.5 3040 3260 3260 3260 3475 250 3975 3475 2275 2437.5 1900 2062.5 3450 1525 1687.5 1150 4775 1312.5 675 837.5 300 462.5 -75 87.5 -450 -287.5 2350 4775 2512.5 1975 2137.5 1600 1762.5 4581.5 4656.5 1225 1387.5 750 2800 4015 4090 3940 3940 3790 3790 3465 3540 3390 3390 7125 -720 699.244 5294.244 1599.527 -824.527 6475.756
5637.5 603 4260 603 3750 603 1275 603 3875 603 4125 603 -50 603 300 603 4702.5 SMDRES805 2570 603 2605 603 2545 603 2485 603 2650 603 1025 603 2650 603 2275 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 1100 603 5637.5 603 5637.5 603 5637.5 603 2150 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 2595 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 5637.5 603 4650 603 4650 603 5637.5 603 5637.5 603 5637.5 603 3675 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 4690 603 3600 TST_PT_PAD50CIR32D 3960 TST_PT_PAD50CIR32D 4275.472 RN4 2824.527 RN4 3849.244 RN4 899.244 RN4 1474.527 RN4
RN103 RN104 RN105 RN106 RN107 RN108 RN109 RN11 RN110 RN111 RN112 RN113 RN114 RN115 RN116 RN117 RN118 RN119 RN12 RN120 RN121 RN122 RN123 RN124 RN125 RN126 RN127 RN128 RN129 RN13 RN130 RN131 RN132 RN133 RN134 RN135 RN136 RN137 RN138 RN139 RN14 RN15 RN16 RN17 RN18 RN19 RN2 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN3 RN30 RN31 RN32 RN33 RN34 RN35 RN36
-824.527 86.744 236.744 6774.244 6775.756 2860.756 2560.756 5124.244 5475.756 6924.244 6474.244 6925.756 6624.244 6625.756 6475.756 6775.756 6925.756 6474.244 -824.527 6624.244 6924.244 6774.244 6625.756 6084.527 6084.527 3850.756 3700.756 3550.756 3400.756 -824.527 3849.244 3699.244 3549.244 3399.244 4069.527 499.527 1425.472 1425.472 1650.472 1650.472 1524.527 -824.527 -824.527 2024.244 3475.472 3974.527 6084.527 6999.244 5749.244 5599.244 5449.244 5299.244 6084.527 5149.244 -513.256 -363.256 -363.256 6084.527 -213.256 4605.472 -825.472 5475.756 6084.527 4605.472 6084.527
749.244 2024.527 2024.527 1250.472 1474.527 2954.527 3174.527 2824.527 2824.527 1250.472 1250.472 1474.527 1250.472 1474.527 2349.527 2349.527 2349.527 2125.472 1199.244 2125.472 2125.472 2125.472 2349.527 939.244 1124.244 1599.527 1599.527 1599.527 1599.527 1799.244 1825.472 1825.472 1825.472 1825.472 1964.244 4079.244 2425.756 2275.756 2275.756 2425.756 1724.244 1649.244 1499.244 1300.472 2374.244 2350.756 1669.244 424.527 2575.472 2575.472 2575.472 2575.472 1819.244 2575.472 2024.527 2024.527 1625.472 1969.244 1625.472 3280.756 1950.756 2825.472 2119.244 3104.244 1519.244
RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4
123 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
RN37 RN38 RN39 RN4 RN40 RN41 RN42 RN43 RN44 RN45 RN46 RN47 RN48 RN49 RN5 RN50 RN51 RN52 RN53 RN54 RN55 RN56 RN57 RN58 RN59 RN6 RN60 RN61 RN62 RN63 RN64 RN65 RN66 RN67 RN68 RN69 RN7 RN70 RN71 RN72 RN73 RN74 RN75 RN76 RN77 RN78 RN79 RN8 RN80 RN81 RN82 RN83 RN84 RN85 RN86 RN87 RN88 RN89 RN9 RN90 RN91 RN92 RN93 RN94 RN95
-825.472 2025.472 575.472 3475.472 575.472 575.472 599.244 449.244 2560.756 2709.244 2860.756 2709.244 4870.472 299.244 3974.527 499.527 499.527 -213.256 749.244 19.527 -405.472 4605.472 4870.472 4870.472 4870.472 -824.527 -180.472 -325.472 -325.472 5199.527 -63.256 150.756 -149.244 6050.472 1599.527 6050.472 221.744 6050.472 -824.527 -600.756 -450.756 -300.756 299.244 449.244 -150.756 574.527 -824.527 5295.756 574.527 -0.756 149.244 -824.527 -825.472 1599.527 2300.756 4605.472 -599.244 2324.244 5125.756 -0.756 1599.527 1599.527 -449.244 -299.244 300.756
2100.756 1475.756 1474.244 2749.244 1624.244 1774.244 3075.472 3075.472 2954.527 2954.527 3174.527 3174.527 3280.756 3075.472 2750.756 3649.244 3824.244 2024.527 3075.472 3899.244 3899.244 3279.244 3104.244 3279.244 3105.756 1349.244 3899.244 4249.244 3574.244 3999.244 2024.527 490.472 490.472 -0.756 4149.244 149.244 1625.472 299.244 900.756 490.472 490.472 490.472 490.472 490.472 490.472 924.244 750.756 2824.527 774.244 490.472 490.472 1050.756 1050.756 3699.244 4599.527 3105.756 490.472 3225.472 2824.527 489.527 4299.244 3549.244 490.472 490.472 490.472
RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4 RN4
RN96 RN97 RN98 RN99 RRDENB RW TDAT0 TP_2.5V TP_3.3V TP_RSTB TP_VCC TP1 TP10 TP100 TP11 TP115 TP117 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP2 TP20 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP3 TP30 TP31 TP32 TP33 TP38 TP39 TP4 TP40 TP41 TP42 TP43 TP45 TP46 TP47 TP48 TP49 TP5 TP50 TP51 TP52 TP53 TP54 TP55 TP56 TP57 TP58 TP59 TP6 TP60 TP61
450.756 574.527 574.527 1599.527 7125 2280 1405 175 5645 2425 3940 5200 670 -625 670 -750 -630 670 1175 2880 2880 2895 2395 2500 2625 2065 4158.5 1600 5425 5100 1600 2125 2625 5425 1765 5300 1965 5000 -650 7125 7205 4200 150 4175 1865 1965 5425 2625 2045 2205 2625 5115 1275 2245 -425 5600 1275 275 700 2725 3960 2980 7195 5625 2300
490.472 RN4 775.756 RN4 925.756 RN4 3999.244 RN4 3450 TST_PT_PAD50CIR32D 3920 TST_PT_PAD50CIR32D 4850 TST_PT_PAD50CIR32D 2825 TST_PT_PAD50CIR32D 300 TST_PT_PAD50CIR32D 2525 TST_PT_PAD50CIR32D 725 TST_PT_PAD50CIR32D 700 TST_PT_PAD50CIR32D 2065 TST_PT_PAD50CIR32D 3075 TST_PT_PAD50CIR32D 2165 TST_PT_PAD50CIR32D 5500 TST_PT_PAD50CIR32D 5500 TST_PT_PAD50CIR32D 2265 TST_PT_PAD50CIR32D 2075 TST_PT_PAD50CIR32D 1705 TST_PT_PAD50CIR32D 1805 TST_PT_PAD50CIR32D 2140 TST_PT_PAD50CIR32D 2145 TST_PT_PAD50CIR32D 925 TST_PT_PAD60CIR36D 4825 TST_PT_PAD60CIR36D 770 TST_PT_PAD50CIR32D 1119 TST_PT_PAD60CIR36D 3175 TST_PT_PAD50CIR32D 4300 TST_PT_PAD50CIR32D 700 TST_PT_PAD50CIR32D 3025 TST_PT_PAD50CIR32D 4850 TST_PT_PAD50CIR32D 725 TST_PT_PAD50CIR32D 4200 TST_PT_PAD50CIR32D 770 TST_PT_PAD50CIR32D 700 TST_PT_PAD50CIR32D 770 TST_PT_PAD50CIR32D 700 TST_PT_PAD50CIR32D 2000 TST_PT_PAD60CIR36D 3775 TST_PT_PAD60CIR36D 2985 TST_PT_PAD60CIR36D 2585 TST_PT_PAD60CIR36D 4700 TST_PT_PAD60CIR36D 5025 TST_PT_PAD60CIR36D 770 TST_PT_PAD50CIR32D 4850 TST_PT_PAD50CIR32D 4100 TST_PT_PAD50CIR32D 825 TST_PT_PAD50CIR32D 4850 TST_PT_PAD50CIR32D 4850 TST_PT_PAD50CIR32D 925 TST_PT_PAD50CIR32D 3850 TST_PT_PAD60CIR36D 750 TST_PT_PAD60CIR36D -60 TST_PT_PAD60CIR36D 2275 TST_PT_PAD60CIR36D 3675 TST_PT_PAD60CIR36D 5175 TST_PT_PAD60CIR36D 2475 TST_PT_PAD60CIR36D 2800 TST_PT_PAD60CIR36D 1250 TST_PT_PAD60CIR36D 2195 TST_PT_PAD60CIR36D 2850 TST_PT_PAD60CIR36D 1015 TST_PT_PAD60CIR36D 4675 TST_PT_PAD60CIR36D 1075 TST_PT_PAD60CIR36D
124 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
TP62 TP63 TP64 TP65 TP68 TP7 TP70 TP71 TP72 TP74 TP75 TP76 TP77 TP78 TP79 TP8 TP80 TP81 TP82 TP86 TP88 TP9 TP99 U1 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U2 U20 U21
2050 2050 1385 1285 2400 570 2300 2400 2400 2400 3075 4025 3825 7025 6200 570 6825 3225 1450 4420 1265 570 -400 5075 2150 3150 2150 3250 -625 -112.5 3375 4965 3375 3450 3725 6320 1075
475 TST_PT_PAD60CIR36D 575 TST_PT_PAD60CIR36D 185 TST_PT_PAD60CIR36D 185 TST_PT_PAD60CIR36D 1075 TST_PT_PAD50CIR32D 2065 TST_PT_PAD50CIR32D 925 TST_PT_PAD60CIR36D 925 TST_PT_PAD60CIR36D 1375 TST_PT_PAD50CIR32D 1225 TST_PT_PAD50CIR32D 1650 TST_PT_PAD50CIR32D 725 TST_PT_PAD50CIR32D 900 TST_PT_PAD60CIR36D 2700 TST_PT_PAD50CIR32D 2600 TST_PT_PAD50CIR32D 2165 TST_PT_PAD50CIR32D 925 TST_PT_PAD60CIR36D 3250 TST_PT_PAD50CIR32D 2680 TST_PT_PAD50CI32D 3770 TST_PT_PAD50CIR32D 2075 TST_PT_PAD50CIR32D 2265 TST_PT_PAD50CIR32D 3075 TST_PT_PAD50CIR32D 1700 SBGA432 3525 PBGA119 550 SO8NB-3 4300 PBGA119 975 SO20WB 2600 DIP8_SOCKET 1300 QFP176 250 SO8NB-3 3560 SO14NB-2 12.5 SOIC8 3925 SBGA_304 2700 QSOP20 3745 SBGA_304 2825 SOT223-3
U22 U23 U25 U26 U27 U3 U31 U4 U5 U6 U7 U8 U9 VDD1 VDD2 VX_DX_D0 VX1_CSB VX1_TCLK WE WR WRDAT0 WRPRTY WTPA Y1 Y2 Y3 Y4 Y5 ZQ1 ZQ2
4823.5 896.5 525 2150 4781.5 3725 1800 3625 6700 6700 775 -480 -465 2735 2735 5425 5600 6300 -640 1565 700 550 375 3665 3125 1700 0 4515 1900 1640
475 1235 5000 2775 4225 2300 1565 1725 2250 1375 3925 3510 4320 4005 3420 3575 3575 2950 3960 4850 4725 4725 2825 746 2300 2775 4975 3585 4675 3390
SSOP5_95 SSOP5_95 SO14NB-2 SO14NB-2 PBGA160 QSOP20 TQFP144-2 TQFP_100-3 TQFP_100-3 TQFP_100-3 SBGA352 TSOP54 TSOP54 JUMPER_3PIN_INLINE JUMPER_3PIN_INLINE TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D TST_PT_PAD50CIR32D CRYS_MA-505 OSC-2 OSC-2 OSC-2 OSC-2 JUMPER_3PIN_INLINE JUMPER_3PIN_INLINE
125 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
22.
APPENDIX I: GLOSSARY ADSL ATM CPLD DSLAM LCD LED LOS LSW LVDS Metadriver MSW NBT SSRAM PCB POTS SDRAM SEEP SONET SSRAM S/UNI Telco UTOPIA VCC VPC Asymmetric Digital Subscriber Line Asynchronous Transfer Mode CMOS Programmable Logic Device Digital Subscriber Line Access Multiplexer Loss of Cell Delineation Light Emitting Diode Loss of Signal Least Significant Word Low Voltage Differential Signal = VORTEX Chipset Driver (card level driver) Most Significant Word No-bus-turnaround Synchronous Static RAM Printed Circuit Board Plain Old Telephony System Synchronous Dynamic Random Access Memory Serial EEPROM Synchronous Optical NETwork Synchronous Static RAM SATURN User Network Interface Telephone Company Universal Test & Operations PHY Interface Virtual Channel Connection Virtual Path Connection
126 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-1990815 ISSUE 4
VORTEX CHIPSET
DSLAM REFERENCE DESIGN: CORE CARD
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Applications Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1990815 (R4) Issue date: December 2000
PMC-SIERRA, INC.
105 - 8555 BAXTER PLACE BURNABY, BC CANADA V5A 4V7 604 .415.6000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

▲Up To Search▲

Price & Availability of 1990815

	To Download 1990815 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .